P89LPC9102_9103_9107_3 © NXP B.V. 2007. All rights reserved.
Product data sheet Rev. 03 — 10 July 2007 31 of 61
NXP Semiconductors
P89LPC9102/9103/9107
8-bit microcontrollers with two-clock accelerated 80C51 core
8.12 I/O ports
The P89LPC9102/9103/9107 has either 6, 7, or 8 I/O pins depending on the reset pin
option and clock source option chosen. Refer to Table 10.
[1] Required for operation above 12 MHz.
8.12.1 Port configurations
All but one I/O port pin on the P89LPC9102/9103/9107 may be configured by software to
one of four types on a bit-by-bit basis. These are: quasi-bidirectional (standard 80C51 port
outputs), push-pull, open drain, and input-only. Two configuration registers for each port
select the output type for each port pin.
P1.5 (RST) can only be an input and cannot be configured.
Fig 14. Interrupt sources, interrupt enables, and power-down wake-up sources (P89LPC9103/9107)
002aaa977
BOF
EBO
KBIF
EKBI
interrupt
to CPU
wake-up
(if in power-down)
EWDRT
CMF
EC
EA (IE0.7)
RTCF
ERTC
(RTCCON.1)
WDOVF
TF1
ET1
TI and RI/RI
ES/ESR
TI
EST
TF0
ET0
ENADCI1
ADCI1
ENBI1
BNDI1
EAD
Table 10. Number of I/O pins available
Clock source Reset option Number of I/O pins
(10-pin package)
Number of I/O pins
(14-pin package)
On-chip oscillator or watchdog
oscillator
No external reset (except during
power-up)
810
External
RST pin supported 7 9
External clock input No external reset (except during
power-up)
79
External
RST pin supported
[1]
68
P89LPC9102_9103_9107_3 © NXP B.V. 2007. All rights reserved.
Product data sheet Rev. 03 — 10 July 2007 32 of 61
NXP Semiconductors
P89LPC9102/9103/9107
8-bit microcontrollers with two-clock accelerated 80C51 core
8.12.2 Quasi-bidirectional output configuration
Quasi-bidirectional output type can be used as both an input and output without the need
to reconfigure the port. This is possible because when the port outputs a logic HIGH, it is
weakly driven, allowing an external device to pull the pin LOW. When the pin is driven
LOW, it is driven strongly and able to sink a fairly large current. These features are
somewhat similar to an open-drain output except that there are three pull-up transistors in
the quasi-bidirectional output that serve different purposes.
The P89LPC9102/9103/9107 is a 3 V device, however, the pins are 5 V-tolerant. In
quasi-bidirectional mode, if a user applies 5 V on the pin, there will be a current flowing
from the pin to V
DD
, causing extra power consumption. Therefore, applying 5 V in
quasi-bidirectional mode is discouraged.
A quasi-bidirectional port pin has a Schmitt triggered input that also has a glitch
suppression circuit.
8.12.3 Open-drain output configuration
The open-drain output configuration turns off all pull-ups and only drives the pull-down
transistor of the port driver when the port latch contains a logic 0. To be used as a logic
output, a port configured in this manner must have an external pull-up, typically a resistor
tied to V
DD
.
An open-drain port pin has a Schmitt triggered input that also has a glitch suppression
circuit.
8.12.4 Input-only configuration
The input-only port configuration has no output drivers. It is a Schmitt triggered input that
also has a glitch suppression circuit.
8.12.5 Push-pull output configuration
The push-pull output configuration has the same pull-down structure as both the
open-drain and the quasi-bidirectional output modes, but provides a continuous strong
pull-up when the port latch contains a logic 1. The push-pull mode may be used when
more source current is needed from a port output. A push-pull port pin has a Schmitt
triggered input that also has a glitch suppression circuit.
8.12.6 Port 0 analog functions
The P89LPC9102/9103/9107 incorporates an Analog Comparator. In order to give the
best analog function performance and to minimize power consumption, pins that are being
used for analog functions must have the digital outputs and digital inputs disabled.
Digital outputs are disabled by putting the port output into the Input-only (high-impedance)
mode as described in Section 8.12.4 “Input-only configuration”.
Digital inputs on Port 0 may be disabled through the use of the PT0AD register. On any
reset, the PT0AD bits default to logic 0s to enable digital functions.
8.12.7 Additional port features
After power-up, all pins are in Input-only mode. Please note that this is different from
the LPC76x series of devices.
P89LPC9102_9103_9107_3 © NXP B.V. 2007. All rights reserved.
Product data sheet Rev. 03 — 10 July 2007 33 of 61
NXP Semiconductors
P89LPC9102/9103/9107
8-bit microcontrollers with two-clock accelerated 80C51 core
After power-up all I/O pins, except P1.5, may be configured by software.
Pin P1.5 is input-only.
Every output on the P89LPC9102/9103/9107 has been designed to sink typical LED drive
current. However, there is a maximum total output current for all ports which must not be
exceeded. Please refer to Table 12 “Static characteristics” for detailed specifications.
All ports pins that can function as an output have slew rate controlled outputs to limit noise
generated by quickly switching output signals. The slew rate is factory-set to
approximately 10 ns rise and fall times.
8.13 Power monitoring functions
The P89LPC9102/9103/9107 incorporates power monitoring functions designed to
prevent incorrect operation during initial power-up and power loss or reduction during
operation. This is accomplished with two hardware functions: Power-on Detect and
Brownout detect.
8.13.1 Brownout detection
The Brownout detect function determines if the power supply voltage drops below a
certain level. The default operation is for a Brownout detection to cause a processor reset,
however, it may alternatively be configured to generate an interrupt.
Brownout detection may be enabled or disabled in software.
If Brownout detection is enabled, the brownout condition occurs when V
DD
falls below the
brownout trip voltage, V
bo
(see Table 12 “Static characteristics”), and is negated when V
DD
rises above V
bo
. If the P89LPC9102/9103/9107 device is to operate with a power supply
that can be below 2.7 V, Brownout detect Enable (BOE) should be left in the
unprogrammed state so that the device can operate at 2.4 V, otherwise continuous
brownout reset may prevent the device from operating.
For correct activation of Brownout detect, the V
DD
rise and fall times must be observed.
Please see Table 12 “Static characteristics” for specifications.
8.13.2 Power-on detection
The Power-on Detect has a function similar to the Brownout detect, but is designed to
work as power comes up initially, before the power supply voltage reaches a level where
Brownout detect can work. The Power-on detect flag (POF) in the RSTSRC register is set
to indicate an initial power-up condition. The POF flag will remain set until cleared by
software.
8.14 Power reduction modes
The P89LPC9102/9103/9107 supports three different power reduction modes. These
modes are Idle mode, Power-down mode, and Total Power-down mode.
8.14.1 Idle mode
Idle mode leaves peripherals running in order to allow them to activate the processor
when an interrupt is generated. Any enabled interrupt source or reset may terminate Idle
mode.

P89LPC9103FTK,115

Mfr. #:
Manufacturer:
NXP Semiconductors
Description:
IC MCU 8BIT 1KB FLASH 10HVSON
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