P89LPC9102_9103_9107_3 © NXP B.V. 2007. All rights reserved.
Product data sheet Rev. 03 — 10 July 2007 34 of 61
NXP Semiconductors
P89LPC9102/9103/9107
8-bit microcontrollers with two-clock accelerated 80C51 core
8.14.2 Slow-down mode using the DIVM register
Slow-down mode is achieved by dividing down the OSCCLK frequency to generate CCLK.
This division is accomplished by configuring the DIVM register to divide OSCCLK by up to
510 times. This feature makes it possible to temporarily run the CPU at a lower rate,
reducing power consumption. By dividing the clock, the CPU can retain the ability to
respond to events that would not exit Idle mode by executing its normal program at a lower
rate. This can also allow bypassing the oscillator start-up time in cases where
Power-down mode would otherwise be used. The value of DIVM may be changed by the
program at any time without interrupting code execution.
8.14.3 Power-down mode
The Power-down mode stops the oscillator in order to minimize power consumption. The
P89LPC9102/9103/9107 exits Power-down mode via any reset, or certain interrupts. In
Power-down mode, the power supply voltage may be reduced to the data retention
voltage V
DDR
. This retains the RAM contents at the point where Power-down mode was
entered. SFR contents are not guaranteed after V
DD
has been lowered to V
DDR
, therefore
it is highly recommended to wake-up the processor via reset in this case. V
DD
must be
raised to within the operating range before the Power-down mode is exited.
Some chip functions continue to operate and draw power during Power-down mode,
increasing the total power used during Power-down mode. These include: Brownout
detect, watchdog timer, comparators (note that comparator can be powered-down
separately), and RTC/system timer. The internal RC oscillator is disabled unless both the
RC oscillator has been selected as the system clock and the RTC is enabled.
8.14.4 Total Power-down mode
This is the same as Power-down mode except that the brownout detection circuitry and
the voltage comparators are also disabled to conserve additional power. The internal RC
oscillator is disabled unless both the RC oscillator has been selected as the system clock
and the RTC is enabled. If the internal RC oscillator is used to clock the RTC during
Power-down mode, there will be high power consumption. Please use an external low
frequency clock to achieve low power with the RTC running during Power-down mode.
8.15 Reset
The P1.5/RST pin can function as either an active-LOW reset input or as a digital input,
P1.5. The RPE (Reset Pin Enable) bit in UCFG1, when set to logic 1, enables the external
reset input function on P1.5. When cleared, P1.5 may be used as an input pin.
Remark: During a power-up sequence, the RPE selection is overridden and this pin will
always function as a reset input. An external circuit connected to this pin should not
hold this pin LOW during a power-on sequence as this will keep the device in reset.
After power-up this input will function either as an external reset input or as a digital input
as defined by the RPE bit. Only a power-up reset will temporarily override the selection
defined by RPE bit. Other sources of reset will not override the RPE bit.
Remark: During a power cycle, V
DD
must fall below V
POR
(see Table 12 “Static
characteristics”) before power is reapplied, in order to ensure a power-on reset.
Reset can be triggered from the following sources:
• External reset pin (during power-up or if user configured via UCFG1)
