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P89LPC9103FTK,115

P1-P3P4-P6P7-P9P10-P12P13-P15P16-P18P19-P21P22-P24P25-P27P28-P30P31-P33P34-P36P37-P39P40-P42P43-P45P46-P48P49-P51P52-P54P55-P57P58-P60P61-P61
P89LPC9102_9103_9107_3 © NXP B.V. 2007. All rights reserved.
Product data sheet Rev. 03 — 10 July 2007 40 of 61
NXP Semiconductors
P89LPC9102/9103/9107
8-bit microcontrollers with two-clock accelerated 80C51 core
taken from the prescaler. The clock source for the prescaler is either the PCLK or the
nominal 400 kHz watchdog oscillator. The watchdog timer can only be reset by a
power-on reset. When the watchdog timer feature is disabled, it can be used as an interval
timer and may generate an interrupt. Figure 17 shows the watchdog timer in Watchdog
mode. Feeding the watchdog timer requires a two-byte sequence. If PCLK is selected as
the watchdog timer clock and the CPU is powered-down, the watchdog timer is disabled.
The watchdog timer has a time-out period that ranges from a few µs to a few seconds.
Please refer to the
P89LPC9102/9103/9107 User manual UM10112
for more details.
8.25 Additional features
8.25.1 Software reset
The SRST bit in AUXR1 gives software the opportunity to reset the processor completely,
as if an external reset or watchdog timer reset had occurred. Care should be taken when
writing to AUXR1 to avoid accidental software resets.
8.25.2 Dual data pointers
The dual Data Pointers (DPTR) provides two different Data Pointers to specify the address
used with certain instructions. The DPS bit in the AUXR1 register selects one of the two
Data Pointers. Bit 2 of AUXR1 is permanently wired as a logic 0 so that the DPS bit may
be toggled (thereby switching Data Pointers) simply by incrementing the AUXR1 register,
without the possibility of inadvertently altering other bits in the register.
(1) Watchdog timer reset can also be caused by an invalid feed sequence, or by writing to WDCON not immediately followed by
a feed sequence.
Fig 17. Watchdog timer in Watchdog mode (WDTE = 1)
PRE2 PRE1 PRE0 - - WDRUN WDTOF WDCLK
WDCON (A7H)
SHADOW REGISTER
PRESCALER
002aaa980
8-BIT DOWN
COUNTER
WDL (C1H)
watchdog
oscillator
PCLK
÷32
MOV WFEED1, #0A5H
MOV WFEED2, #05AH
reset (1)
P89LPC9102_9103_9107_3 © NXP B.V. 2007. All rights reserved.
Product data sheet Rev. 03 — 10 July 2007 41 of 61
NXP Semiconductors
P89LPC9102/9103/9107
8-bit microcontrollers with two-clock accelerated 80C51 core
8.26 Flash program memory
8.26.1 General description
The P89LPC9102/9103/9107 flash memory provides in-circuit electrical erasure and
programming. The flash can be erased, read, and written as bytes. The Sector and Page
Erase functions can erase any flash sector (256 bytes) or page (16 bytes). The Chip
Erase operation will erase the entire program memory. In-Circuit Programming using
standard commercial programmers is available. In addition, In-Application Programming
Lite (IAP-Lite) and byte erase allows code memory to be used for non-volatile data
storage. On-chip erase and write timing generation contribute to a user-friendly
programming interface. The P89LPC9102/9103/9107 flash reliably stores memory
contents even after more than 400000 erase and program cycles. The cell is designed to
optimize the erase and programming mechanisms. The P89LPC9102/9103/9107 uses
V
DD
as the supply voltage to perform the Program/Erase algorithms.
8.26.2 Features
• Programming and erase over the full operating voltage range.
• Byte-erase allowing code memory to be used for data storage.
• Read/Programming/Erase using ICP.
• Any flash program/erase operation in 2 ms.
• Programming with industry-standard commercial programmers.
• Programmable security for the code in the flash for each sector.
• More than 400000 minimum erase/program cycles for each byte.
• 20-year minimum data retention.
8.26.3 Flash organization
The P89LPC9102/9103/9107 program memory consists of four 256 byte sectors. Each
sector can be further divided into 16-byte pages. In addition to sector erase, page erase,
and byte erase, a 16-byte page register is included which allows from 1 byte to 16 bytes of
a given page to be programmed at the same time, substantially reducing overall
programming time. In addition, erasing and reprogramming of user-programmable
configuration bytes including UCFG1, the Boot Status Bit, and the Boot Vector is
supported.
8.26.4 Flash programming and erasing
Different methods of erasing or programming of the flash are available. The flash may be
programmed or erased in the end-user application (IAP-Lite) under control of the
application’s firmware. Another option is to use the ICP mechanism. This ICP system
provides for programming through a serial clock- serial data interface. Third, the flash may
be programmed or erased using a commercially available EPROM programmer which
supports this device. This device does not provide for direct verification of code memory
contents. Instead this device provides a 32-bit CRC result on either a sector or the entire
1 kB of user code space.
P89LPC9102_9103_9107_3 © NXP B.V. 2007. All rights reserved.
Product data sheet Rev. 03 — 10 July 2007 42 of 61
NXP Semiconductors
P89LPC9102/9103/9107
8-bit microcontrollers with two-clock accelerated 80C51 core
8.26.5 In-circuit programming
In-Circuit Programming is performed without removing the microcontroller from the
system. The In-Circuit Programming facility consists of internal hardware resources to
facilitate remote programming of the P89LPC9102/9103/9107 through a two-wire serial
interface. The NXP In-Circuit Programming facility has made in-circuit programming in an
embedded application, using commercially available programmers, possible with a
minimum of additional expense in components and circuit board area. The ICP function
uses five pins. Only a small connector needs to be available to interface your application
to a commercial programmer in order to use this feature. Additional details may be found
in the
P89LPC9102/9103/9107 User manual UM10112
.
8.26.6 In-application programming (IAP-Lite)
In-Application Programming is performed in the application under the control of the
microcontroller’s firmware. The IAP facility consists of internal hardware resources to
facilitate programming and erasing. The NXP In-Application Programming (IAP-Lite) has
made in-application programming in an embedded application possible without additional
components. This is accomplished through the use of four SFRs consisting of a
control/status register, a data register, and two address registers. Additional details may
be found in the
P89LPC9102/9103/9107 User manual UM10112
.
8.26.7 Using flash as data storage
The flash code memory array of this device supports individual byte erasing and
programming. Any byte in the code memory array may be read using the MOVC
instruction, provided that the sector containing the byte has not been secured (a MOVC
instruction is not allowed to read code memory contents of a secured sector). Thus any
byte in a non-secured sector may be used for non-volatile data storage.
8.26.8 User configuration bytes
Some user-configurable features of the P89LPC9102/9103/9107 must be defined at
power-up and therefore cannot be set by the program after start of execution. These
features are configured through the use of the flash byte UCFG1. Please see the
P89LPC9102/9103/9107 User manual UM10112
for additional details.
8.26.9 User sector security bytes
There are four user sector security bytes, each corresponding to one sector. Please see
the
P89LPC9102/9103/9107 User manual UM10112
for additional details.
P1-P3P4-P6P7-P9P10-P12P13-P15P16-P18P19-P21P22-P24P25-P27P28-P30P31-P33P34-P36P37-P39P40-P42P43-P45P46-P48P49-P51P52-P54P55-P57P58-P60P61-P61

P89LPC9103FTK,115

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Manufacturer:
NXP Semiconductors
Description:
IC MCU 8BIT 1KB FLASH 10HVSON
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