P3041 Features
P3041 QorIQ Communications Processor Product Brief, Rev. 0
Freescale Semiconductor 11
parallel address paths allow for high address bandwidth, which is a key performance indicator for
large coherent multicore processors
• Eliminates address retries, triggered by CPUs being unable to snoop within the narrow snooping
window of a shared bus. This results in the P3041 having lower average memory latency
The flexible P3041’s 36-bit, physical address map consists of local space and external address space. For
the local address map, 32 local access windows (LAWs) define mapping within the local 36-bit (64-Gbyte)
address space. Inbound and outbound translation windows can map the P3041 into a larger system address
space such as the RapidIO or PCIe 64-bit address environment. This functionality is included in the
address translation and mapping units (ATMUs).
3.8 Memory Complex
The P3041 memory complex consists of one DDR controller for main memory, and the memory
controllers associated with the Enhanced Local Bus Controller (eLBC).
3.8.1 DDR Memory Controller
The P3041 DDR memory controllers have the following functionalities:
• Supports DDR3/3L SDRAM. The P3041 also supports chip-select interleaving within a controller.
• The P3041 can be configured to retain the currently active SDRAM page for pipelined burst
accesses. Page mode support of up to 32 simultaneously open pages can dramatically reduce access
latencies for page hits. Depending on the memory system design and timing parameters, page mode
can save up to 10 memory clock cycles for subsequent burst accesses that hit in an active page.
• Using ECC, the P3041 detects and corrects all single-bit errors and detects all double-bit errors and
all errors within a nibble.
• Upon detection of a loss of power signal from external logic, the DDR controllers can put
compliant DDR SDRAM DIMMs into self-refresh mode, allowing systems to implement
battery-backed main memory protection.
• Supports initialization bypass feature for use by system designers to prevent re-initialization of
main memory during system power-on after an abnormal shutdown
• Supports active zeroization of system memory upon detection of a user-defined security violation
3.8.2 PreBoot Loader (PBL) and Nonvolatile Memory Interfaces
The PreBoot Loader (PBL) is a new logic module that operates similarly to an I
2
C boot sequencer but on
behalf of a larger number of interfaces.
The PBL’s functions include the following:
• Simplifies boot operations, replacing pin strapping resistors with configuration data loaded from
nonvolatile memory
• Uses the configuration data to initialize other system logic and to copy data from low speed
memory interfaces (I
2
C, eLBC, SPI, and SD/MMC) into fully initialized DDR or the 1-Mbyte
front-side cache.
