P3041 QorIQ Communications Processor Product Brief, Rev. 0
P3041 Multicore Processing Options
Freescale Semiconductor4
Figure 4 shows an additional use case, which involves the use of one of the CPUs as an I/O processor. The
DPAA can greatly simplify and accelerate processing for packets entering the system by means of the
All CPUs are running a single operating system, with any specialization of CPU
function occurring through OS techniques such as Task Affinity. The I/Os and
acceleration hardware are under the control of the SMP OS. Typically all CPUs
operate at the same frequency.
Some number of the cores are operated as an SMP cluster, most likely running
high complexity control plane operations. The control plane configures and
manages the remaining processors, which are running individual copies of an
RTOS or scheduler to perform dataplane operations. In this use case, the SMP
CPUs typically operate at the same frequency, the remaining CPUs can run at a
different frequency from the SMP CPUs, and even from each other.
A single CPU is used as the control processor, configuring and managing the
other three processors, which are running individual copies of an RTOS or
scheduler, as in B. CPU operating frequencies are an independent parameter.
All CPUs are used for datapath operations, here shown as two sets of pipelined
functions, each interacting independently with the I/Os and accelerators.
Operating frequencies for each CPU in the pipeline can be set independently, and
the provision of a 128-Kbyte back-side L2 provides significant flexibility in
partitioning and rebalancing the pipeline as processing requirements change.
Figure 3. CPU Usage Use Cases
