P3041 Features
P3041 QorIQ Communications Processor Product Brief, Rev. 0
Freescale Semiconductor 25
3.12.4 Secure Boot and Sensitive Data Protection
The e500mc MMUs and PAMU allow the P3041 to enforce a consistent set of memory access permissions
on a per-partition basis. When combined with embedded Hypervisor for safe sharing of resources, the
P3041 becomes highly resilient when poorly tested or malicious code is run. For system developers
building high reliability/high security platforms, rigorous testing of code of known origin is the norm.
3.12.4.1 Secure Boot Option
The system developer digitally signs the code to be executed by the CPU coming out of reset, and the
P3041 ensures that only an unaltered version of that code runs on the platform. The P3041 offers both boot
time and run time code authenticity checking and configurable consequences when the authenticity check
fails.
3.12.4.2 Sensitive Data Protection Option
The P3041 supports protected internal and external storage of developer-provisioned sensitive instructions
and data.
For example, a system developer may provision each system with a number of RSA private keys to be used
in mutual authentication and key exchange. These values would initially be stored in external non-volatile
memory, but following secure boot, these values can be decrypted into on-chip protected memory (portion
of platform cache dedicated as SRAM). Session keys, which may number in the thousands to tens of
thousands, are not good candidates for on-chip storage, so the P3041 offers session key encryption.
Session keys are stored in main memory, and are decrypted (transparently to software and without
impacting SEC throughput) as they are brought into the SEC 4.2 for decryption of session traffic.
3.13 Advanced Power Management
The P3041’s advanced power management capabilities are based around fine-grained static clock control
and software-controlled dynamic frequency management.
3.13.1 Saving Power by Managing Internal Clocks
Dynamic voltage and frequency scaling (DVFS) are useful techniques for reducing typical/average power
and maximizing battery life in laptop environments, but embedded applications must be designed for rapid
response to bursts of traffic and max power under worst-case environmental conditions. While the P3041
does not implement DVFS in the PC sense, it does actively manage internal clocks to avoid wasting
energy. Clock signals are disabled to idle components, reducing dynamic power. These blocks can return
to full operating frequency on the clock cycle after work is dispatched to them.
The P3041 also supports (under software control) dynamic changes to CPU operating frequencies and
voltages. Each CPU sources its input clock from one of two independent PLLs inside the P3041. Each CPU
can also source its input clock from an integer frequency divider from two of the three independent PLLs.
CPUs can switch their source PLL, and their frequency divider glitchlessly and nearly instantaneously.
This allows each core to operate at the minimum frequency required to perform its assigned function,
saving power.
