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P3041NXE7MMC

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P3041 QorIQ Communications Processor Product Brief, Rev. 0
P3041 Features
Freescale Semiconductor22
Figure 7. SEC 4.2 Block Diagram
3.11.4.5 Pattern Matching Engine (PME 2.1)
The PME is a self-contained hardware module capable of autonomously scanning data from streams for
patterns that match a specification in a database dedicated to it. The PME 2.1 is an updated version of the
PME used in previous members of the PowerQUICC family. Specific updates include the following:
• QMan interface supporting the DPAA Queue Interface Driver
• 2x increase in the number of patterns supported (16 Kbytes to 32 Kbytes)
• Increase in number of stateful rules supported (8 Kbytes to 16 Kbytes)
• Raw scanning performance is ~ 5 Gbps.
Patterns that can be recognized, or “matched,” by the PME are of two general forms:
• Byte patterns are simple matches such as “abcd123” existing in both the data being scanned and in
the pattern specification database.
• Event patterns are a sequence of multiple byte patterns. In the PME, event patterns are defined by
stateful rules.
3.11.4.5.1 PME Regular Expressions (Regex)
The PME specifies patterns of bytes as regular expressions (regex). The P3041 (by means of an online or
offline process) converts Regex patterns into the PME’s pattern specification database. Generally, there is
a one-to-one mapping between a regex and a PME byte pattern. The PME’s use of regex pattern matching
offers built-in case-insensitivity and wildcard support with no pattern explosion, while the PME’s
NFA-style architecture offers fast pattern database compilation and fast incremental updates. Up to 32,000
regex patterns are supported, each up to 128 bytes long. The 32,000 regex patterns can be combined by
means of stateful rules to detect a far larger set of event patterns. Comparative compilations against DFA
style regex engines have shown that 300,000 DFA pattern equivalents can be achieved with ~8000 PME
regexes with stateful rules.
Job Queue
Controller
On-Chip
System
Interface
Queue Manager
Interface
Descriptor
Controllers
RTIC
CHAs
P3041 Features
P3041 QorIQ Communications Processor Product Brief, Rev. 0
Freescale Semiconductor 23
3.11.4.5.2 PME Match Detection
Within the PME, match detection proceeds in stages. The key element scanner performs initial byte pattern
matching, with handoff to the data examination engine for elimination of false positives through more
complex comparisons. As the name implies, the stateful rule engine receives confirmed basic matches
from the earlier stages, and monitors a stream for addition for subsequent matches that define an event
pattern.
Figure 8. PME 2.1 Block Diagram
3.12 Avoiding Resource Contentions Using
the QorIQ Trust Architecture
Consolidation of discrete CPUs into a single, multicore SoC and potential repartitioning of legacy software
on those cores introduces many opportunities for unintended resource contentions to arise, but the QorIQ
Trust Architecture can reduce the risk of these issues.
3.12.1 QorIQ Trust Architecture Benefits
A system may exhibit erratic behavior if the multiple CPUs do not effectively partition and share system
resources. While it can be challenging to prevent unintended resource contention, stopping malicious
software is much more difficult. Device consolidation combined with a trend toward embedded systems
becoming more open (or more likely to run third-party or open-source software on at least one of the cores)
creates opportunities for malicious code to enter a system.
The P3041 offers a new level of hardware partitioning support, allowing system developers to ensure
software running on any CPU only accesses the resources (memory, peripherals, etc.) that it is explicitly
authorized to access. This may not seem like a challenge in an SMP environment, because the OS performs
resource allocation for the applications running on it. However, it is a very difficult problem to overcome
in AMP environments where there may be multiple instances of the same OS, or even different OSes
running on the various CPU cores. Even OS protections in an SMP system may be insufficient in the
presence of malicious software.
Results
Stateful
Rule
Engine
(SRE)
Data
Examination
Engine
(DXE)
Key
Element
Scanning
Engine
(KES)
Hash
Ta bl e s
DMA
(Queue/
Buffer
Manager
Interfaces)
On-Chip
System
Interface
Access to Pattern Descriptions and State
P3041 QorIQ Communications Processor Product Brief, Rev. 0
P3041 Features
Freescale Semiconductor24
3.12.2 e500mc MMU and Embedded Hypervisor
The P3041’s first line of defense against unintended interactions amongst the multiple CPUs/OSes is each
e500mc core’s MMU, which are configured to determine which addresses in the global address map the
CPU is able to read or write. If a particular resource (such as a portion of memory or a peripheral device)
is dedicated to a single CPU, that CPU’s MMU is configured to allow access to those addresses (on
4-Kbyte granularity); other CPU MMUs are not configured for access to the other CPU’s private memory
range. When two CPUs need to share resources, both of their MMUs are configured to have access to the
shared address range.
This level of hardware support for partitioning is common today; however, it is not sufficient for many
core systems running diverse software. When the functions of multiple discrete CPUs are consolidated
onto a single multicore SoC, achieving strong partitioning shouldn’t require the developer to map
functions onto cores that are the exclusive owners of specific platform resources. The alternative, a fully
open system with no private resources, is also unacceptable. For this reason, the e500mc MMU also
includes embedded Hypervisor extensions.
Each e500mc MMU supports three levels of instructions:
•User
• Supervisor (OS)
• Hypervisor: An embedded Hypervisor micro-kernel (provided by Freescale as source code) runs
unobtrusively beneath the various OSes running on the CPUs, consuming CPU cycles only when
an access attempt is made to an embedded Hypervisor-managed shared resource.The embedded
Hypervisor determines whether the access should be allowed, and if so, proxies the access on
behalf of the original requestor. If malicious or poorly tested software on any core attempts to
overwrite important device configuration registers (including CPU MMUs), the embedded
Hypervisor blocks the write. Other examples of embedded Hypervisor managed resources are
high- and low-speed peripheral interfaces (PCIe, UART) if those resources are not dedicated to a
single CPU/partition.
3.12.3 Peripheral Access Management Unit (PAMU)
The P3041 includes a distributed function collectively referred to as the peripheral access management
unit (PAMU), which provides address translation and access control for all bus masters in the system
(PME, SEC, FMan, and so on). The PAMU access control can be one of the following:
• Absolute—The FMan, PME, SEC, and other bus masters can never access memory range XYZ.
• Conditional—Based on the Partition ID of the CPU that programmed the bus master
Being MMU-based, the embedded Hypervisor is only able to stop unauthorized software access attempts.
Internal components with bus mastering capability also need to be prevented from reading and writing to
specific memory regions. These devices do not spontaneously generate access attempts, but, if
programmed to do so by buggy or malicious software, any of them could overwrite sensitive configuration
registers and crash the system.
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P3041NXE7MMC

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NXP / Freescale
Description:
Microprocessors - MPU P3041 -40-105C WE1200 R2
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