P3041NXE7MMC Datasheet P3041NXN7MMC, P3041NSE7NNC, P3041NXE7NNC | P13-P15

P3041 Features

P3041 QorIQ Communications Processor Product Brief, Rev. 0

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3.9 Universal Serial Bus (USB) 2.0

The two USB 2.0 controllers with integrated PHY provide point-to-point connectivity complying with the

USB specification, Rev. 2.0. Each USB controller can be configured to operate as a stand-alone host, and

USB #2 can be configured as a stand-alone device, or with both host and device functions operating

simultaneously.

Key features of the USB 2.0 controller include the following:

• Complies with USB specification, Rev. 2.0

• Supports high-speed (480 Mbps), full-speed (12 Mbps), and low-speed (1.5 Mbps) operations

• Supports the required signaling for the USB transceiver macrocell interface (UTMI).The PHY

interfacing to the UTMI is an internal PHY.

• Both controllers support operation as a stand-alone USB host controller

— Support USB root hub with one downstream-facing port

— Enhanced host controller interface (EHCI)-compatible

• One controller supports operation as a stand-alone USB device

— Supports one upstream-facing port

— Supports six programmable USB endpoints

The host and device functions are both configured to support all four USB transfer types:

• Bulk

• Control

• Interrupt

• Isochronous

3.10 High-Speed Peripheral Interface Complex

All high-speed peripheral interfaces connect via 18 lanes of 5-GHz SerDes to a common crossbar switch

referred to as OCeaN. Two high-speed I/O interface standards are supported: PCI Express (PCIe), and

Serial RapidIO (sRIO). The P3041 integrates the following:

• Four PCIe controllers

• Two Serial RapidIO controllers

• RapidIO message manager (RMan).

3.10.1 PCI Express Controllers

Each of the four PCIe interfaces is compliant with the PCI Express Base Specification Revision 2.0. Key

features of the PCIe interface include the following:

• Power-on reset configuration options allow root complex or endpoint functionality.

• The physical layer operates at 2.5 or 5 Gbaud data rate per lane.

• Receive and transmit ports operate independently, with an aggregate theoretical bandwidth of 32

Gbps.

P3041 QorIQ Communications Processor Product Brief, Rev. 0

P3041 Features

Freescale Semiconductor14

• x8, x4, x2, and x1 link widths supported

• Both 32- and 64-bit addressing and 256-byte maximum payload size

• Full 64-bit decode with 36-bit wide windows

• Inbound INTx transactions

• Message Signaled Interrupt (MSI) transactions

3.10.2 Serial RapidIO Interfaces

3.10.2.1 Serial RapidIO Interface

The Serial RapidIO interface is based on the RapidIO Interconnect Specification, Revision 1.3 with

features from 2.1. RapidIO is a high-performance, point-to-point, low-pin-count, packet-switched

system-level interconnect that can be used in a variety of applications as an open standard. The rich feature

set includes high data bandwidth, low-latency capability, and support for high-performance I/O devices as

well as message-passing and software-managed programming models. Receive and transmit ports operate

independently, and with 2 x 4 Serial RapidIO controllers, the aggregate theoretical bandwidth is 32 Gbps.

Key features of the Serial RapidIO interface unit include the following:

• Support for RapidIO Interconnect Specification, Revision 1.3 (all transaction flows and priorities)

• 1x, 2x, and 4x LP-serial link interfaces, with transmission rates of 2.5, 3.125, or 5.0 Gbaud (data

rates of 2.0, 2.5, or 4.0 Gbps) per lane.

• Auto-detection of 1x, 2x, or 4x mode operation during port initialization

• 34-bit addressing and up to 256-byte data payload

• Receiver-controlled flow control

• RapidIO error injection

• Internal LP-serial and application interface-level loopback modes

3.10.2.2 RapidIO Message Manager (RMan)

The key features of the RapidIO message manager (RMan) include the following:

• Manages two inbox/outbox mailboxes (queues) for data and one doorbell message structure

• Can multi-cast a single-segment 256-byte message to up to 32 different destination DevIDs

• Has four outbound segmentation units supporting RapidIO Type 5–6 and Type 8–11

3.10.3 Serial ATA (SATA) 2.0 Controllers

The key features of each of the two SATA include the following:

• Designed to comply with Serial ATA 2.6 Specification

• Supports host SATA I per spec Rev 1.0a

— OOB

— Port multipliers

P3041 Features

P3041 QorIQ Communications Processor Product Brief, Rev. 0

Freescale Semiconductor 15

— ATAPI 6+

— Spread spectrum clocking on receive

• Support for SATA II extensions

— Asynchronous notification

— Hot plug including asynchronous signal recovery

— Link power management

— Native command queuing

— Staggered spin-up and port multiplier support

• Support for SATA I and II data rates (1.5 and 3.0 Gbaud)

• Standard ATA master-only emulation

• Includes ATA shadow registers

• Implements SATA superset registers (SError, SControl, SStatus)

• Interrupt driven

• Power management support

• Error handling and diagnostic features

— Far end/near end loopback

— Failed CRC error reporting

— Increased ALIGN insertion rates

— Scrambling and CONT override

3.11 Data Path Acceleration Architecture (DPAA)

The DPAA provides the infrastructure to support simplified sharing of networking interfaces and

accelerators by multiple CPU cores. These resources are abstracted into enqueue/dequeue operations by

means of a common DPAA Queue Manager (QMan) driver. Beyond enabling multicore resource sharing,

the DPAA significantly reduces software overheads associated with high-touch packet-forwarding

operations. Examples of the types of packet-processing services this architecture is optimized to support

are as follows:

• Traditional routing and bridging

• Firewall

• VPN termination for both IPsec and SSL VPNs

• Intrusion detection/prevention (IDS/IPS)

• Network anti-virus (AV)

The DPAA generally leaves software in control of protocol processing, while reducing CPU overheads

through off-load functions, which fall into two, broad categories:

• Section 3.11.1, “Packet Distribution and Queue/Congestion Management”

• Section 3.11.2, “Accelerating Content Processing”

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