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P3041NXE7MMC

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P3041 Features
P3041 QorIQ Communications Processor Product Brief, Rev. 0
Freescale Semiconductor 7
— CoreNet fabric supporting coherent and non-coherent transactions with prioritization and
bandwidth allocation amongst CoreNet end-points
— Queue manager fabric supporting packet-level queue management and quality of service
scheduling
• One 64-bit DDR3/3L SDRAM memory controller with ECC and chip-select interleaving support
• Data Path Acceleration Architecture (DPAA) incorporating acceleration for the following
functions:
— Frame management for packet parsing, classification, and distribution
— Queue management for scheduling, packet sequencing, and congestion management
— Hardware buffer management for buffer allocation and de-allocation
— Encryption/decryption (SEC 4.2)
— RegEx pattern matching (PME 2.1)
— RapidIO™ messaging manager (RMan)
• Ethernet interfaces
— One 10 Gbps Ethernet (XAUI) controller
— Five 1 Gbps or four 2.5 Gbps Ethernet controllers
• High speed peripheral interfaces
— Four PCI Express 2.0 controllers/ports running at up to 5 GHz
— Two Serial RapidIO® controllers/ports (version 1.3 with features of 2.1) running at up to
5 GHz
– RapidIO message manager (RMan) with Type 5–6 and Type 8–11 support
— Dual SATA 2.0 interfaces
• Additional peripheral interfaces
— Two USB 2.0 controllers with integrated PHY
— SD/MMC controller (eSDHC)
— Enhanced SPI controller
— Four I
2
C controllers
— Dual DUARTs
— Dual SATA supporting 1.5 and 3.0 Gb/s operation
• 18 SerDes lanes to 5 GHz
• Enhanced local bus controller (eLBC)
• Multicore programmable interrupt controller (MPIC)
• Two 4-channel DMA engines
3.3 P3041 Benefits
The P3041’s e500mc cores can be combined as a fully-symmetric, multi-processing, system-on-a-chip, or
they can be operated with varying degrees of independence to perform asymmetric multi-processing. Full
processor independence, including the ability to independently boot and reset each e500mc core, is a
P3041 QorIQ Communications Processor Product Brief, Rev. 0
P3041 Features
Freescale Semiconductor8
defining characteristic of the P3041. The ability of the cores to run different operating systems, or run
OS-less, provides the user with significant flexibility in partitioning between control, datapath, and
applications processing. It also simplifies consolidation of functions previously spread across multiple
discrete processors onto a single device.
3.4 Data Path Acceleration Architecture (DPAA) Benefits
While the four Power Architecture cores offer a major leap in available processor performance in many
throughput-intensive, packet-processing networking applications, raw processing power is not enough to
achieve multi-Gbps data rates. To address this, the P3041 uses Freescale’s Data Path Acceleration
Architecture (DPAA) (see Section 3.11, “Data Path Acceleration Architecture (DPAA)”), which
significantly reduces data plane instructions per packet, enabling more CPU cycles to work on value-added
services rather than repetitive low-level tasks. Combined with specialized accelerators for cryptography
and pattern matching, the P3041 allows the user’s software to perform complex packet processing at high
data rates.
3.5 P3041 Critical Performance Parameters
Table 1 lists key performance indicators that define a set of values used to measure P3041 operation.
Table 1. P3041 Critical Performance Parameters
Indicator Values(s)
Top speed bin e500mc
core frequency
1.5 GHz
Maximum memory data
rates
1.3 GHz (DDR3/3L)
1
• 1.5-V for DDR3
• 1.35-V for DDR3L
Notes:
1
Conforms to JEDEC standard
Local bus • 3.3 V
• 2.5 V
•1.8V
Operating junction
temperature range
0–105 C with the option for –40 to 105 C
Package • 1295-pin FC-PBGA (flip-chip plastic ball grid array)
• Pin-compatible with P4040, P4080, P5010, and P5020
P3041 Features
P3041 QorIQ Communications Processor Product Brief, Rev. 0
Freescale Semiconductor 9
3.6 e500mc Core and Cache Memory Complex
The P3041 offers four high-performance, 32-bite500mc cores based on the Power Architecture® from
Power ISA 2.06. Like previous e500 cores, each e500mc is a superscalar dual issue processor, supporting
out-of-order execution and in-order completion.
3.6.1 e500mc Features Summary
Key features of the e500mc include the following:
• Up to 1.5 GHz core clock speed
• 36 bit physical addressing
• 64 TLB SuperPages
• 512-entry, 4-Kbyte pages front-end
• 128-Kbyte backside L2 cache supporting ECC single-bit error correction
• 3 Integer units
—Two simple
— One complex (integer multiply and divide)
• 64-byte cache line
• L1 caches, running at same frequency as CPU
— 32-Kbyte Instruction, 8 way
— 32-Kbyte Data, 8 way
— Both with data and tag parity protection
• Supports Data Path Acceleration Architecture (DPAA) data and context “stashing” into frontside
cache
• User, Supervisor, and Hypervisor instruction level privileges
• New processor facilities
— Hardware support for efficient partitioning and virtualization
— Double-precision floating-point unit
– Complies with IEEE Std. 754™
– Binary-compatible with e300 and e600
– Supports 32 64-bit floating point registers for scalar single- and double-precision
floating-point arithmetic. Decorated storage facility to provide additional atomic operations
of up to two 64-bit quantities by a single access including a “fire and forget” APU for
improved statistics support
— Expanded interrupt model
– Improved programmable interrupt controller (PIC) automatically ACKs interrupts
– Implements message send and receive functions for interprocessor communication,
including receive filtering
— External PID load and store facility
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P3041NXE7MMC

Mfr. #:
Buy P3041NXE7MMC
Manufacturer:
NXP / Freescale
Description:
Microprocessors - MPU P3041 -40-105C WE1200 R2
Lifecycle:
New from this manufacturer.
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