P3041 QorIQ Communications Processor Product Brief, Rev. 0
P3041 Features
Freescale Semiconductor16
3.11.1 Packet Distribution and Queue/Congestion Management
Table 2 lists some packet distribution and queue/congestion management offload functions.
3.11.2 Accelerating Content Processing
Properly implemented acceleration logic can provide significant performance advantages over most
optimized software with acceleration factors on the order of 10–100x. Accelerators in this category
typically touch most of the bytes of a packet (not just headers). To avoid consuming CPU cycles in order
to move data to the accelerators, these engines include well-pipelined DMAs. Table 3 lists some specific
content-processing accelerators on the P3041.
Table 2. P3041 Offload Functions
Function Type Definition
Data buffer
management
Supports allocation and deallocation of buffers belonging to pools originally created by software with
configurable depletion thresholds. Implemented in a module called the Buffer Manager (BMan).
Queue
management
Supports queuing and quality-of-service scheduling of frames to CPUs, network interfaces and DPAA logic
blocks, maintains packet ordering within flows. Implemented in a module called the Queue Manager
(QMan). The QMan, besides providing flow-level queuing, is also responsible for congestion management
functions such as RED/WRED, congestion notifications and tail discards.
Packet distribution Supports in-line packet parsing and general classification to enable policing and QoS-based packet
distribution to the CPUs for further processing of the packets. This function is implemented in the block
called the Frame Manager (FMan).
Policing Supports in-line rate-limiting by means of two-rate, three-color marking (RFC 2698). Up to 256 policing
profiles are supported. This function is also implemented in the FMan.
Table 3. P3041 Content-Processing Accelerators
Interface Definition
SEC 4.2 Crypto-acceleration for protocols such as IPsec, SSL, and 802.16
PME 2.1 Regex style pattern matching for unanchored searches, including cross-packet stateful patterns
Note: Prior versions of the SEC and PME are integrated into multiple members of the PowerQUICC and QorIQ family. Both of
these engines have been enhanced to work within the DPAA, and also upgraded in both features and performance.
