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SerDes flexibility makes it possible to enable up to 14 Gbps full duplex of Ethernet traffic on the FMan,
however, the FMan can support line rate parsing and classification on an aggregate of 12 Gbps.
3.11.4.1.2 FMan Parse Function
The primary function of the packet parse logic is to identify the incoming frame for the purpose of
determining the desired treatment to apply. This parse function can parse many standard protocols,
including options and tunnels, and supports a generic configurable capability to allow proprietary or future
protocols to be parsed.
There are several types of parser headers, shown in Table 5.
The underlying notion is that different frames may require different treatment, and only through detailed
parsing of the frame can proper treatment be determined.
Parse results can (optionally) be passed to software.
3.11.4.1.3 FMan Distribution and Policing
After parsing is complete, there are two options for treatment (see Table 6).
Key benefits of the FMan policing function are as follows:
Table 5. Parser Header Types
Header Type Definition
Self-describing Announced by proprietary values of Ethertype, protocol identifier, next header, and other standard fields.
They are self-describing in that the frame contains information that describes the presence of the
proprietary header.
Non-self-describing Does not contain any information that indicates the presence of the header.
For example, a frame that always contains a proprietary header before the Ethernet header would be
non-self-describing. Both self-describing and non-self-describing headers are supported by means of
parsing rules in the FMan.
Proprietary Can be defined as being self-describing or non-self-describing
Table 6. Post-Parsing Treatment Options
Treatment Function Benefits
Hash Hashes selected fields in the frame as part of a spreading mechanism
The result is a specific frame queue identifier.
To support added control, this FQID can be indexed by values found in the frame,
such as TOS or p-bits, or any other desired field(s).
Useful when spreading
traffic while obeying QoS
constraints is required
Classification
look-up
Looks up certain fields in the frame to determine subsequent action to take,
including policing
The FMan contains internal memory that holds small tables for this purpose.
The user configures the sets of lookups to perform, and the parse results dictate
which one of those sets to use.
Lookups can be chained together such that a successful look-up can provide key
information for a subsequent look-up. After all the look-ups are complete, the final
classification result provides either a hash key to use for spreading, or a FQ ID
directly.
Useful when hash
distribution is insufficient
and a more detailed
examination of the frame
is required
Can determine whether
policing is required and
the policing context to use
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Because the FMan has up to 256 policing profiles, any frame queue or group of frame queues can
be policed to either drop or mark packets if the flow exceeds a preconfigured rate.
Policing and classification can be used in conjunction for mitigating Distributed Denial of Service
Attack (DDOS).
The policing is based on two-rate-three-color marking algorithm (RFC2698). The sustained and
peak rates as well as the burst sizes are user-configurable. Hence, the policing function can
rate-limit traffic to conform to the rate the flow is mapped to at flow set-up time. By prioritizing
and policing traffic prior to software processing, CPU cycles can be focused on the important and
urgent traffic ahead of other traffic.
3.11.4.2 Queue Manager (QMan)
The Queue Manager (QMan) is the main component in the DPAA that allows for simplified sharing of
network interfaces and hardware accelerators by multiple CPU cores. It also provides a simple and
consistent message and data passing mechanism for dividing processing tasks amongst multiple CPU
cores. The QMan features are as follows:
Common interface between software and all hardware
Controls the prioritized queuing of data between multiple processor cores, network interfaces,
and hardware accelerators
Supports both dedicated and pool channels, allowing both push and pull models of multicore
load spreading
Atomic access to common queues without software locking overhead
Mechanisms to guarantee order preservation with atomicity and order restoration following
parallel processing on multiple CPUs
Two-level queuing hierarchy with one or more Channels per Endpoint, eight work queues per
Channel, and numerous frame queues per work queue
Priority and work conserving fair scheduling between the work queues and the frame queues
Loss-less flow control for ingress network interfaces
Congestion avoidance (RED/WRED) and congestion management with tail discard and up to 256
congestion groups with each group composed of a user-configured number of frame queues.
3.11.4.3 Buffer Manager (BMan)
The buffer manager (BMan) manages pools of buffers on behalf of software for both hardware
(accelerators and network interfaces) and software use. The BMan features are as follows:
Common interface for software and hardware
Guarantees atomic access to shared buffer pools
Supports 32 buffer pools. Software and hardware buffer consumers can request both different size
buffers and buffers in different memory partitions.
Supports depletion thresholds with congestion notifications
On-chip per pool buffer stockpile to minimize access to memory for buffer pool management
LIFO (last in first out) buffer allocation policy that optimizes cache usage and allocation
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Freescale Semiconductor 21
3.11.4.4 Security Engine (SEC 4.2)
The SEC 4.2 is QorIQ’s fourth generation crypto-acceleration engine. In addition to off-loading
cryptographic algorithms, the SEC 4.2 offers header and trailer processing for several established security
protocols. The SEC 4.2 includes several Descriptor Controllers (DECOs), which are updated versions of
the previous SEC crypto-channels. DECOs are responsible for header and trailer processing, and
managing context and data flow into the CHAs assigned to it for the length of an operation.
The DECOs can perform header and trailer processing, as well as single pass encryption/integrity checking
for the following security protocols:
•IPsec
SSL/TLS
•SRTP
IEEE Std 802.1AE™ MACSec
IEEE 802.16e WiMax MAC layer
3GPP RLC encryption/decryption
In prior versions of the SEC, the individual algorithm accelerators were referred to as Execution Units
(EUs). In the SEC 4.2, these are referred to as Crypto Hardware Accelerators (CHAs) to distinguish them
from prior implementations. Specific CHAs available to the DECOs are listed below.
Advanced encryption standard unit (AESA)
ARC four execution unit (AFHA)
Cyclic redundancy check accelerator (CRCA)
Data encryption standard execution unit (DESA)
Kasumi execution unit (KFHA)
SNOW 3 G hardware accelerator (STHA)
Message digest execution unit (MDHA)
Public key execution unit (PKHA)
Random number generator (RNGB)
Depending on the security protocol and specific algorithms, the SEC 4.2’s aggregate symmetric
encryption/integrity performance is 5 Gbps, while asymmetric encryption (RSA public key) performance
is ~5,000 1024b RSA operations per second.
The SEC 4.2 is also part of the QorIQ Trust Architecture, which gives the P3041 the ability to perform
secure boot, runtime code integrity protection, and session key protection. The Trust Architecture is
described in Section 3.12, “Avoiding Resource Contentions Using the QorIQ Trust Architecture.”

P3041NXE7MMC

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NXP / Freescale
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Microprocessors - MPU P3041 -40-105C WE1200 R2
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