IP4855CX25 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2013. All rights reserved.
Product data sheet Rev. 2 — 24 May 2013 13 of 30
NXP Semiconductors
IP4855CX25
SD 3.0-compliant memory card integrated dual voltage level translator
12.2 ESD characteristic of pin write protect and card detect
[1] TLP according to ANSI-ESD STM5.5.1/IEC 62615 Z
o
=50; pulse width = 100 ns; rise time = 200 ps;
averaging window = 50 ns to 80 ns
13. Application information
The IP4855CX25 is optimized to connect SD 3.0 and SD 2.0 compatible memory cards to
1.8 V base band/host interfaces. While the internal I/O interface towards the memory card
is supplied by the IP4855CX25 integrated voltage regulator, any connected memory card
has to be supplied from an external source. Using for example DDR50 or SDR50 modes
requires a power supply with up to 400 mA DC current capabilities.
Place IP4855CX25 as close as possible to the card holder to minimize the influence of
trace length on the timing values. The trace length between IP4855CX25 and the card
has a much bigger influence on the timing than the identical length between the host
interface and the IP4855CX25.
Table 12. ESD characteristic of write protect and card detect
At recommended operating conditions; T
amb
=+25
C; voltages are referenced to
GND (ground = 0 V); unless otherwise specified
Symbol Parameter Conditions Min Typ Max Unit
ESD protection pins: WP and CD
V
BR
breakdown voltage TLP; I = 1 mA - 8 - V
r
dyn
dynamic resistance positive transient
[1]
-0.5-
negative transient
[1]
-0.5-
