IP4855CX25 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2013. All rights reserved.
Product data sheet Rev. 2 — 24 May 2013 22 of 30
NXP Semiconductors
IP4855CX25
SD 3.0-compliant memory card integrated dual voltage level translator
PCB Z
o
=25, trace length = 100 mm, t
PD
= maximum, slow driver model
Fig 12. Detailed description of a DDR50 read cycle, worst case timing
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IP4855CX25 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2013. All rights reserved.
Product data sheet Rev. 2 — 24 May 2013 23 of 30
NXP Semiconductors
IP4855CX25
SD 3.0-compliant memory card integrated dual voltage level translator
14. Test information
Definitions test circuit:
R
source
= source resistance of pulse generator.
R
term
= termination resistance should be equal to output impedance Z
o
of pulse generator.
C
L
= load capacitance including jig and probe capacitance.
R
L
= load resistance.
Fig 13. Load circuitry for measuring switching time
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IP4855CX25 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2013. All rights reserved.
Product data sheet Rev. 2 — 24 May 2013 24 of 30
NXP Semiconductors
IP4855CX25
SD 3.0-compliant memory card integrated dual voltage level translator
15. Package outline
Fig 14. Package outline IP4855CX25 (WLCSP25)
wlcsp25_5x5_po
European
projection
WLCSP25: wafer level chip-size package; 25 bumps (5 x 5)
bump A1
index area
D
E
X
detail X
A
A
2
A
1
e
1
e
1
e
e
b
E
D
C
B
A
12345
Table 16. Dimensions of IP4855CX25 for Figure 14
Symbol Min Typ Max Unit
A 0.44 0.47 0.50 mm
A
1
0.18 0.20 0.22 mm
A
2
0.25 0.27 0.29 mm
b 0.21 0.26 0.31 mm
D 1.99 2.04 2.09 mm
E 1.99 2.04 2.09 mm
e-0.4-mm

IP4855CX25Z

Mfr. #:
Manufacturer:
Nexperia
Description:
Translation - Voltage Levels SD 3.0-Compliant Memory Card
Lifecycle:
New from this manufacturer.
Delivery:
DHL FedEx Ups TNT EMS
Payment:
T/T Paypal Visa MoneyGram Western Union

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