IP4855CX25 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2013. All rights reserved.
Product data sheet Rev. 2 — 24 May 2013 22 of 30
NXP Semiconductors
IP4855CX25
SD 3.0-compliant memory card integrated dual voltage level translator
PCB Z
o
=25, trace length = 100 mm, t
PD
= maximum, slow driver model
Fig 12. Detailed description of a DDR50 read cycle, worst case timing
LQYDOLG LQYDOLG
(0,),/7(5
&/.B6'
+267
,17(5)$&(
,2
,2
))
))
,2%8))(
5
GDWD LQYDOLG LQYDOLG LQYDOLGGDWD
GDWD GDWD GDWD
6'&$5'
(0,),/7(5
&/.B,1
&/.B)%
',5B;
DDD
W
3'
+RVWVLGHSLQV&/.B,1WR&/.B)%
W
3'
0HPRU\FDUGVLGHLQSXWVWR
KRVWVLGHRXWSXWV
W
2'/<[
2XWSXWGHOD\WLPHGXULQJGDWDWUDQVIHUPRGH
6HH6'SK\VLFDOOD\HUVSHFLILFDWLRQIRUGHWDLOV
&/.B6'
&/.B)%
&/.B,1
KRVW
'$7$>@
6'RXWSXW
'$7$>@
KRVWLQSXW
W
2'/<;PD[
QV
,IDULVLQJHGJHRI&/.B,1LVXVHGWRWULJJH
U
DUHDGWKHDFWXDOGDWDLVUHDGLQWRWKHKRVW
RQWKHIROORZLQJIDOOLQJ&/.B)%HGJH
''5UHDGPRGHZRUVWFDVHWLPLQJ
QV
QV
QV
GDWD
LQYDOLG
,3&;
&0'B6'
'$7$B>@B6'
&0'B+
'$7$>@B+