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IP4855CX25Z

P1-P3P4-P6P7-P9P10-P12P13-P15P16-P18P19-P21P22-P24P25-P27P28-P30
IP4855CX25 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2013. All rights reserved.
Product data sheet Rev. 2 — 24 May 2013 4 of 30
NXP Semiconductors
IP4855CX25
SD 3.0-compliant memory card integrated dual voltage level translator
7. Pinning information
7.1 Pinning
7.2 Pin description
Fig 3. Pin configuration WLCSP25
Table 2. Pin allocation table
Pin Symbol Pin Symbol Pin Symbol Pin Symbol Pin Symbol
A1 DATA2_H A2 DIR_CMD A3 DIR_0 A4 V
SUPPLY
A5 DATA2_SD
B1 DATA3_H B2 SEL B3 V
CCA
B4 V
LDO
B5 DATA3_SD
C1 CLK_IN C2 ENABLE C3 GND C4 V
SD_REF
C5 CLK_SD
D1 DATA0_H D2 CMD_H D3 CD D4 CMD_SD D5 DATA0_SD
E1 DATA1_H E2 CLK_FB E3 DIR_1_3 E4 WP E5 DATA1_SD
008aaa193
transparent top view,
solder balls facing down
D
B
E
C
A
24135
bump A1
index area
Table 3. Pin description
Symbol
[1]
Pin Type
[2]
Description
DATA2_H A1 I/O data 2 input or output on host side
DIR_CMD A2 I direction control input for command
DIR_0 A3 I direction control input for data 0
V
SUPPLY
A4 S supply voltage (from battery or regulator)
DATA2_SD A5 I/O data 2 input or output on memory card side
DATA3_H B1 I/O data 3 input or output on host side
SEL B2 I card side I/O voltage level select
V
CCA
B3 S supply voltage from host side
V
LDO
B4 O internal supply decoupling
DATA3_SD B5 I/O data 3 input or output on memory card side
IP4855CX25 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2013. All rights reserved.
Product data sheet Rev. 2 — 24 May 2013 5 of 30
NXP Semiconductors
IP4855CX25
SD 3.0-compliant memory card integrated dual voltage level translator
[1] The pin names relate particularly to SD memory cards, but also apply to microSD and MMC memory cards.
[2] I = input, O = output, I/O = input and output, S = power supply
8. Functional description
8.1 Level translator
The bidirectional level translator shifts the data between the I/O supply levels of the host
and the memory card. Dedicated direction control signals determine if a command and
data signals are transferred from the memory card to the host (card read mode) or from
the host to the memory card (card write mode). The voltage translator has to support
several clock and data transfer rates at the signaling levels specified in the SD 3.0
standard specification.
CLK_IN C1 I clock signal input on host side
ENABLE C2 I device enable input
GND C3 S supply ground
V
SD_REF
C4 I reference voltage for the internal voltage regulator
CLK_SD C5 O clock signal output on memory card side
DATA0_H D1 I/O data 0 input or output on host side
CMD_H D2 I/O command input or output on host side
CD D3 O card detect switch biasing output
CMD_SD D4 I/O command input or output on memory card side
DATA0_SD D5 I/O data 0 input or output on memory card side
DATA1_H E1 I/O data 1 input or output on host side
CLK_FB E2 O clock feedback output on host side
DIR_1_3 E3 I direction control input for data 1, data 2, data 3
WP E4 O write protect switch biasing output
DATA1_SD E5 I/O data 1 input or output on memory card side
Table 3. Pin description
…continued
Symbol
[1]
Pin Type
[2]
Description
Table 4. Supported modes
Bus speed mode Signal level (V) Clock rate (MHz) Data rate (MB/s)
Default-Speed 3.3 25 12.5
High-Speed 3.3 50 25
SDR12 1.8 25 12.5
SDR25 1.8 50 25
SDR50 1.8 100 50
DDR50 1.8 50 50
IP4855CX25 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2013. All rights reserved.
Product data sheet Rev. 2 — 24 May 2013 6 of 30
NXP Semiconductors
IP4855CX25
SD 3.0-compliant memory card integrated dual voltage level translator
8.2 Enable and direction control
The pin ENABLE enables/disables the Low DropOut (LDO) and is used to put the
host-side, card-side I/O drivers into high-ohmic 3-state mode.
[1] H = HIGH; L = LOW and X = don’t care.
8.3 Integrated voltage regulator
The low dropout voltage regulator delivers supply voltage for the voltage translators and
the card-side input/output stages. It has to support 1.8 V and 3 V signaling modes as
stipulated in the SD 3.0 specification. The switching time between the two output voltage
modes is compliant with SD 3.0 specification. Depending on the signaling level at pin
SEL, the regulator delivers 1.8 V (SEL = HIGH) or 2.9 V (SEL = LOW, V
SD_REF
<1 V). For
card supply voltage, see Section 8.4
.
[1] H = HIGH and L = LOW.
[2] Host-side pins are not influenced by SEL.
Table 5. I/O function control signal truth table
Control Host-side Memory card-side
Pin Level
[1]
Pin Function Pin Function
Pin ENABLE = HIGH and V
CCA
1.62 V
DIR_CMD H CMD_H input CMD_SD output
L CMD_H output CMD_SD input
DIR_0 H DATA0_H input DATA0_SD output
L DATA0_H output DATA0_SD input
DIR_1_3 H DATA1_H
DATA2_H
DATA3_H
input DATA1_SD
DATA2_SD
DATA3_SD
output
LDATA1_H
DATA2_H
DATA3_H
output DATA1_SD
DATA2_SD
DATA3_SD
input
- - CLK_IN input CLK_SD output
- - CLK_FB output - -
Pin ENABLE = LOW or V
CCA
0.8 V
DIR_CMD X CMD_H high-ohmic CMD_SD high-ohmic
DIR_0 X DATA0_H high-ohmic DATA0_SD high-ohmic
DIR_1_3 X DATA1_H
DATA2_H
DATA3_H
high-ohmic DATA1_SD
DATA2_SD
DATA3_SD
high-ohmic
- - CLK_IN input CLK_SD high-ohmic
- - CLK_IN high-ohmic - -
Table 6. SD card side voltage level control signal truth table
Input Output
SEL
[1]
V
SD_REF
V
LDO
Pin
[2]
Function
H irrelevant 1.8 V DATA0_SD to DATA3_SD, CLK_SD low supply voltage level (1.8 V
typ
)
L < 1 V 2.9 V DATA0_SD to DATA3_SD, CLK_SD high supply voltage level (2.9 V
typ
)
>1.5V V
SD_REF
DATA0_SD to DATA3_SD, CLK_SD supply voltage level based on V
SD_REF
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IP4855CX25Z

Mfr. #:
Buy IP4855CX25Z
Manufacturer:
Nexperia
Description:
Translation - Voltage Levels SD 3.0-Compliant Memory Card
Lifecycle:
New from this manufacturer.
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