IP4855CX25 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2013. All rights reserved.
Product data sheet Rev. 2 — 24 May 2013 20 of 30
NXP Semiconductors
IP4855CX25
SD 3.0-compliant memory card integrated dual voltage level translator
In contrast to the write cycle, the read cycle is more complex to analyze and depends on
the IP4855CX25 delay, the maximum delay added by the PCB and the additional setup
time of the SD card.
The same mechanism is triggered on each falling clock edge too, as the DDR50 mode
uses both edges of the clock signal for data transfer.
According to the SD 3.01 physical layer specification, the maximum delay between
CLK_IN (CLK_SD signal) at the SD card and data out from the SD card (DATA[3:0]_SD
out) is 7.0 ns. This value is specified for a load of C
L
25 pF.
Table 15. DDR50 read mode: parameters for best case and worst case timings
Parameter Best case timing (Figure 11) Worst case timing (Figure 12)
PCB output impedance Z
o
65 25
Symmetrical trace length 15 mm per side 100 mm per side
t
PD
minimum maximum
Driver model fast slow
