SST49LF008A-33-4C-NHE Datasheet SST49LF008A-33-4C-NHE, SST49LF008A-33-4C-NHE-T, SST49LF008A-33-4C-WHE | P10-P12

8 Mbit Firmware Hub

SST49LF008A

Data Sheet

Microchip Technology Company

Figure 6: Single-Byte Read Waveforms

Table 3: FWH Read Cycle

Clock

Cycle

Field

Name

Field Contents

FWH[3:0]

Direction Comments

1 START 1101 IN FWH4 must be active (low) for the part to respond. Only the

last start field (before FWH4 transitions high) should be recog-

nized. The START field contents indicate a FWH memory

Read cycle.

2 IDSEL 0000 to 1111 IN Indicates which FWH device should respond. If the to IDSEL (ID

select) field matches the value ID[3:0], then that particular device will

respond to the whole bus cycle.

3-9 IMADDR YYYY IN These seven clock cycles make up the 28-bit memory address.

YYYY is one nibble of the entire address. Addresses are trans-

ferred most-significant nibble first.

10 IMSIZE 0000 (1 byte) IN A field of this size indicates how many bytes will be or trans-

ferred during multi-byte operations. The SST49LF008A will only

support single-byte operation. IMSIZE=0000b

11 TAR0 1111 IN

then Float

In this clock cycle, the master (Intel ICH) has driven the bus

then float to all ‘1’s and then floats the bus, prior to the next

clock cycle. This is the first part of the bus “turnaround cycle.”

12 TAR1 1111 (float) Float

then OUT

The SST49LF008A takes control of the bus during this cycle.

During the next clock cycle, it will be driving “sync data.”

13 RSYNC 0000 (READY) OUT During this clock cycle, the FWH will generate a “ready-sync”

(RSYNC) indicating that the least-significant nibble of the least-

significant byte will be available during the next clock cycle.

14 DATA YYYY OUT YYYY is the least-significant nibble of the least-significant data byte.

15 DATA YYYY OUT YYYY is the most-significant nibble of the least-significant data byte.

16 TAR0 1111 OUT

then Float

In this clock cycle, the SST49LF008A has driven the bus to all

ones and then floats the bus prior to the next clock cycle. This

is the first part of the bus “turnaround cycle.”

17 TAR1 1111 (float) Float then

The master (Intel ICH) resumes control of the bus during this

cycle.

T3.3 25085

1. Field contents are valid on the rising edge of the present clock cycle.

CLK

FWH4

FWH[3:0]

1161 F09.0

STR TAR RSYNCIMSIMADDRIDS DA TA T AR

8 Mbit Firmware Hub

SST49LF008A

Data Sheet

Microchip Technology Company

Figure 7: Write Waveforms

Table 4: FWH Write Cycle

Clock

Cycle

Field

Name

Field Contents

FWH[3:0]

Direction Comments

1 START 1110 IN FWH4 must be active (low) for the part to respond. Only

the last start field (before FWH4 transitions high) should

be recognized. The START field contents indicate a FWH

memory Read cycle.

2 IDSEL 0000 to 1111 IN Indicates which SST49LF008A device should respond.

If the IDSEL (ID select) field matches the value

ID[3:0], then that particular device will respond to the

whole bus cycle.

3-9 IMADDR YYYY IN These seven clock cycles make up the 28-bit memory

address. YYYY is one nibble of the entire address.

Addresses are transferred most-significant nibble first.

10 IMSIZE 0000 (1 byte) IN This size field indicates how many bytes will be trans-

ferred during multi-byte operations. The FWH only

supports single-byte writes. IMSIZE=0000b

11 DATA YYYY IN This field is the least-significant nibble of the data byte.

This data is either the data to be programmed into the

flash memory or any valid flash command.

12 DATA YYYY IN This field is the most-significant nibble of the data byte.

13 TAR0 1111 IN then Float In this clock cycle, the master (Intel ICH) has driven the

then float bus to all ‘1’s and then floats the bus prior to

the next clock cycle. This is the first part of the bus “turn-

around cycle.”

14 TAR1 1111 (float) Float then OUT The SST49LF008A takes control of the bus during this

cycle. During the next clock cycle it will be driving the

“sync” data.

15 RSYNC 0000 OUT The SST49LF008A outputs the values 0000, indicating

that it has received data or a flash command.

16 TAR0 1111 OUT then Float In this clock cycle, the SST49LF008A has driven the bus

to all then float ‘1’s and then floats the bus prior to the

next clock cycle. This is the first part of the bus “turn-

around cycle.”

17 TAR1 1111 (float) Float then IN The master (Intel ICH) resumes control of the bus during this

cycle.

T4.4 25085

1. Field contents are valid on the rising edge of the present clock cycle.

CLK

FWH4

FWH[3:0]

1161 F10.0

STR DA TA T ARTA R

RSYNC

IMSIMADDRIDS

8 Mbit Firmware Hub

SST49LF008A

Data Sheet

Microchip Technology Company

Abort Mechanism

If FWH4 is driven low for one or more clock cycles during a FWH cycle, the cycle will be terminated

and the device will wait for the ABORT command. The host may drive the FWH[3:0] with ‘1111b’

(ABORT command) to return the device to Ready mode. If abort occurs during a Write operation, the

data may be incorrectly altered.

Response To Invalid Fields

During FWH operations, the FWH will not explicitly indicate that it has received invalid field sequences.

The response to specific invalid fields or sequences is as follows:

Address out of range:

The FWH address sequence is 7 fields long (28 bits), but only the last five address fields (20 bits) will

be decoded by SST49LF008A.

Address A

has the special function of directing reads and writes to the flash core (A

=1) or to the

=0).

Invalid IMSIZE field:

If the FWH receives an invalid size field during a Read or Write operation, the device will reset and no

operation will be attempted. The SST49LF008A will not generate any kind of response in this situation.

Invalid-size fields for a Read/Write cycle are anything but 0000b.

Device Memory Hardware Write Protection

The Top Boot Lock (TBL#) and Write Protect (WP#) pins are provided for hardware write protection of

device memory in the SST49LF008A. The TBL# pin is used to write protect 16 boot sectors (64 KByte)

at the highest flash memory address range for the SST49LF008A. WP# pin write protects the remain-

ing sectors in the flash memory.

An active low signal at the TBL# pin prevents Program and Erase operations of the top boot sectors.

When TBL# pin is held high, write protection of the top boot sectors is then determined by the Boot

Block Locking register. The WP# pin serves the same function for the remaining sectors of the device

memory. The TBL# and WP# pins write protection functions operate independently of one another.

Both TBL# and WP# pins must be set to their required protection states prior to starting a Program or

Erase operation. A logic level change occurring at the TBL# or WP# pin during a Program or Erase

operation could cause unpredictable results. TBL# and WP# pins cannot be left unconnected.

TBL# is internally OR’ed with the top Boot Block Locking register. When TBL# is low, the top Boot

Block is hardware write protected regardless of the state of the Write-Lock bit for the Boot Block Lock-

ing register. Clearing the Write-Protect bit in the register when TBL# is low will have no functional

effect, even though the register may indicate that the block is no longer locked.

WP# is internally OR’ed with the Block Locking register. When WP# is low, the blocks are hardware

write protected regardless of the state of the Write-Lock bit for the corresponding Block Locking regis-

ters. Clearing the Write-Protect bit in any register when WP# is low will have no functional effect, even

though the register may indicate that the block is no longer locked.

P1-P3 P4-P6 P7-P9 P10-P12 P13-P15 P16-P18 P19-P21 P22-P24 P25-P27 P28-P30 P31-P33 P34-P36 P37-P39 P40-P42 P43-P45

SST49LF008A-33-4C-NHE

Mfr. #:

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Manufacturer:

Microchip Technology

Description:

NOR Flash 8M (1Mx8) 33MHz Commercial Temp

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SST49LF008A-33-4C-NHE

SST49LF008A-33-4C-NHE

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