©2011 Silicon Storage Technology, Inc. DS25085A 10/11
8
8 Mbit Firmware Hub
SST49LF008A
Data Sheet
Microchip Technology Company
Design Considerations
SST recommends a high frequency 0.1 µF ceramic capacitor to be placed as close as possible
between V
DD
and V
SS
less than 1 cm away from the V
DD
pin of the device. Additionally, a low fre-
quency 4.7 µF electrolytic capacitor from V
DD
to V
SS
should be placed within 1 cm of the V
DD
pin. If you
use a socket for programming purposes add an additional 1-10 µF next to each socket.
The RST# pin must remain stable at V
IH
for the entire duration of an Erase operation. WP# must
remain stable at V
IH
for the entire duration of the Erase and Program operations for non-Boot Block
sectors. To write data to the top Boot Block sectors, the TBL# pin must also remain stable at V
IH
for the
entire duration of the Erase and Program operations.
Product Identification
The product identification mode identifies the device as the SST49LF008A and manufacturer as SST.
Mode Selection
The SST49LF008A flash memory devices can operate in two distinct interface modes: the Firmware
Hub Interface (FWH) mode and the Parallel Programming (PP) mode. The IC (Interface Configuration
pin) is used to set the interface mode selection. If the IC pin is set to logic High, the device is in PP
mode; while if the IC pin is set Low, the device is in the FWH mode. The IC selection pin must be con-
figured prior to device operation. The IC pin is internally pulled down if the pin is not connected. In
FWH mode, the device is configured to interface with its host using Intel’s Firmware Hub proprietary
protocol. Communication between Host and the SST49LF008A occurs via the 4-bit I/O communication
signals, FWH [3:0] and the FWH4. In PP mode, the device is programmed via an 11-bit address and
an 8-bit data I/O parallel signals. The address inputs are multiplexed in row and column selected by
control signal R/C# pin. The column addresses are mapped to the higher internal addresses, and the
row addresses are mapped to the lower internal addresses. See the Device Memory Map in Figure 5
for address assignments.
Table 2: Product Identification
Byte Data
JEDEC ID
Address
Location
Manufacturer’s ID 0000H BFH FFBC0000H
Device ID
SST49LF008A 0001H 5AH FFBC0001H
T2.7 25085
