©2011 Silicon Storage Technology, Inc. DS25085A 10/11
29
8 Mbit Firmware Hub
SST49LF008A
Data Sheet
Microchip Technology Company
AC Characteristics (PP Mode)
Table 21:Read Cycle Timing Parameters, V
DD
=3.0-3.6V (PP Mode)
Symbol Parameter Min Max Units
T
RC
Read Cycle Time 270 ns
T
RST
RST# High to Row Address Setup 1 µs
T
AS
R/C# Address Set-up Time 45 ns
T
AH
R/C# Address Hold Time 45 ns
T
AA
Address Access Time 120 ns
T
OE
Output Enable Access Time 60 ns
T
OLZ
OE# Low to Active Output 0 ns
T
OHZ
OE# High to High-Z Output 35 ns
T
OH
Output Hold from Address Change 0 ns
T21.2 25085
Table 22:Program/Erase Cycle Timing Parameters, V
DD
=3.0-3.6V (PP Mode)
Symbol Parameter Min Max Units
T
RST
RST# High to Row Address Setup 1 µs
T
AS
R/C# Address Setup Time 50 ns
T
AH
R/C# Address Hold Time 50 ns
T
CWH
R/C# to Write Enable High Time 50 ns
T
OES
OE# High Setup Time 20 ns
T
OEH
OE# High Hold Time 20 ns
T
OEP
OE# to Data# Polling Delay 40 ns
T
OET
OE# to Toggle Bit Delay 40 ns
T
WP
WE# Pulse Width 100 ns
T
WPH
WE# Pulse Width High 100 ns
T
DS
Data Setup Time 50 ns
T
DH
Data Hold Time 5 ns
T
IDA
Software ID Access and Exit Time 150 ns
T
BP
Byte Programming Time 20 µs
T
SE
Sector-Erase Time 25 ms
T
BE
Block-Erase Time 25 ms
T
SCE
Chip-Erase Time 100 ms
T22.2 25085
Table 23:Reset Timing Parameters, V
DD
=3.0-3.6V (PP Mode)
Symbol Parameter Min Max Units
T
PRST
V
DD
stable to Reset Low 1 ms
T
RSTP
RST# Pulse Width 100 ns
T
RSTF
RST# Low to Output Float 48 ns
T
RST
1
1. There will be a reset latency of T
RSTE
or T
RSTC
if a reset procedure is performed during a Program or Erase operation.
RST# High to Row Address Setup 1 µs
T
RSTE
RST# Low to reset during Sector-/Block-Erase or Program 10 µs
T
RSTC
RST# Low to reset during Chip-Erase 50 µs
T23.1 25085
