©2011 Silicon Storage Technology, Inc. DS25085A 10/11
6
8 Mbit Firmware Hub
SST49LF008A
Data Sheet
Microchip Technology Company
Table 1: Pin Description
Symbol Pin Name Type
1
Interface
FunctionsPP FWH
A
10
-A
0
Address I X Inputs for low-order addresses during Read and Write opera-
tions. Addresses are internally latched during a Write cycle. For
the programming interface, these addresses are latched by R/
C# and share the same pins as the high-order address inputs.
DQ
7
-DQ
0
Data I/O X To output data during Read cycles and receive input data during
Write cycles. Data is internally latched during a Write cycle. The
outputs are in tri-state when OE# is high.
OE# Output Enable I X To gate the data output buffers
WE# Write Enable I X To control the Write operations
IC Interface
Configuration
Pin
I X X This pin determines which interface is operational. When held
high, programmer mode is enabled and when held low, FWH
mode is enabled. This pin must be setup at power-up or before
return from reset and not change during device operation. This pin
is internally pulled- down with a resistor between 20-100 K
INIT# Initialize I X This is the second reset pin for in-system use. This pin is inter-
nally combined with the RST# pin; If this pin or RST# pin is
driven low, identical operation is exhibited.
ID[3:0] Identification
Inputs
I X These four pins are part of the mechanism that allows multiple
parts to be attached to the same bus. The strapping of these
pins is used to identify the component.The boot device must
have ID[3:0]=0000 and it is recommended that all subsequent
devices should use sequential up-count strapping. These pins
are internally pulled-down with a resistor between 20-100 K
FGPI[4:0] General Pur-
pose Inputs
I X These individual inputs can be used for additional board flexibil-
ity. The state of these pins can be read through GPI_REG regis-
ter. These inputs should be at their desired state before the start
of the PCI clock cycle during which the read is attempted, and
should remain in place until the end of the Read cycle. Unused
GPI pins must not be floated.
TBL# Top Block Lock I X When low, prevents programming to the Boot Block sectors at top of
memory. When TBL# is high it disables hardware write protection for
the top block sectors. This pin cannot be left unconnected.
FWH[3:0] FWH I/Os I/O X I/O Communications
CLK Clock I X To provide a clock input to the control unit
FWH4 FWH Input I X Input Communications
RST# Reset I X X To reset the operation of the device
WP# Write Protect I X When low, prevents programming to all but the highest address-
able blocks. When WP# is high it disables hardware write protec-
tion for these blocks. This pin cannot be left unconnected.
R/C# Row/Column
Select
I X Select For the Programming interface, this pin determines whether
the address pins are pointing to the row addresses, or to the column
addresses.
RES Reserved X These pins must be left unconnected.
V
DD
Power Supply PWR X X To provide power supply (3.0-3.6V)
V
SS
Ground PWR X X Circuit ground (OV reference) All V
SS
pins must be grounded.
NC No Connection I X X Unconnected pins
T1.4 25085
1. I = Input, O = Output
