©2011 Silicon Storage Technology, Inc. DS25085A 10/11
19
8 Mbit Firmware Hub
SST49LF008A
Data Sheet
Microchip Technology Company
Write Operation Status Detection
The SST49LF008A device provides two software means to detect the completion of a Write (Program
or Erase) cycle, in order to optimize the system Write cycle time. The software detection includes two
status bits: Data# Polling (DQ
7
) and Toggle Bit (DQ
6
). The End-of-Write detection mode is enabled
after the rising edge of WE# which initiates the internal Program or Erase operation.
The actual completion of the nonvolatile write is asynchronous with the system; therefore, either a
Data# Polling or Toggle Bit read may be simultaneous with the completion of the Write cycle. If this
occurs, the system may possibly get an erroneous result, i.e., valid data may appear to conflict with
either DQ
7
or DQ
6
. In order to prevent spurious rejection, if an erroneous result occurs, the software
routine should include a loop to read the accessed location an additional two (2) times. If both reads
are valid, then the device has completed the Write cycle, otherwise the rejection is valid.
Data# Polling (DQ
7
)
When the SST49LF008A device is in the internal Program operation, any attempt to read DQ
7
will pro-
duce the complement of the true data. Once the Program operation is completed, DQ
7
will produce
true data. Note that even though DQ
7
may have valid data immediately following the completion of an
internal Write operation, the remaining data outputs may still be invalid: valid data on the entire data
bus will appear in subsequent successive Read cycles after an interval of 1 µs. During internal Erase
operation, any attempt to read DQ
7
will produce a ‘0’. Once the internal Erase operation is completed,
DQ
7
will produce a ‘1’. The Data# Polling is valid after the rising edge of fourth WE# pulse for Program
operation. For Sector- or Chip-Erase, the Data# Polling is valid after the rising edge of sixth WE# pulse.
See Figure 15 for Data# Polling timing diagram and Figure 26 for a flowchart. Proper status will not be
given using Data# Polling if the address is in the invalid range.
Toggle Bit (DQ
6
)
During the internal Program or Erase operation, any consecutive attempts to read DQ
6
will produce
alternating ‘0’s and ‘1’s, i.e., toggling between 0 and 1. When the internal Program or Erase operation
is completed, the toggling will stop. The device is then ready for the next operation. The Toggle Bit is
valid after the rising edge of fourth WE# pulse for Program operation. For Sector-, Block- or Chip-
Erase, the Toggle Bit is valid after the rising edge of sixth WE# pulse. See Figure 16 for Toggle Bit tim-
ing diagram and Figure 26 for a flowchart.
