©2011 Silicon Storage Technology, Inc. DS25085A 10/11
13
8 Mbit Firmware Hub
SST49LF008A
Data Sheet
Microchip Technology Company
Reset
AV
IL
on INIT# or RST# pin initiates a device reset. INIT# and RST# pins have the same function inter-
nally. It is required to drive INIT# or RST# pins low during a system reset to ensure proper CPU initial-
ization.
During a Read operation, driving INIT# or RST# pins low deselects the device and places the output
drivers, FWH[3:0], in a high-impedance state. The reset signal must be held low for a minimal duration
of time T
RSTP.
A reset latency will occur if a reset procedure is performed during a Program or Erase
operation. See Table 19, Reset Timing Parameters for more information. A device reset during an
active Program or Erase will abort the operation and memory contents may become invalid due to data
being altered or corrupted from an incomplete Erase or Program operation.
Write Operation Status Detection
The SST49LF008A device provides two software means to detect the completion of a Write (Program
or Erase) cycle, in order to optimize the system Write cycle time. The software detection includes two
status bits: Data# Polling (DQ
7
) and Toggle Bit (DQ
6
). The End-of-Write detection mode is incorpo-
rated into the FWH Read cycle. The actual completion of the nonvolatile write is asynchronous with the
system; therefore, either a Data# Polling or Toggle Bit read may be simultaneous with the completion
of the Write cycle. If this occurs, the system may possibly get an erroneous result, i.e., valid data may
appear to conflict with either DQ
7
or DQ
6
. In order to prevent spurious rejection, if an erroneous result
occurs, the software routine should include a loop to read the accessed location an additional two (2)
times. If both reads are valid, then the device has completed the Write cycle, otherwise the rejection is
valid.
Data# Polling (DQ
7
)
When the SST49LF008A device is in the internal Program operation, any attempt to read DQ
7
will pro-
duce the complement of the true data. Once the Program operation is completed, DQ
7
will produce
true data. Note that even though DQ
7
may have valid data immediately following the completion of an
internal Write operation, the remaining data outputs may still be invalid: valid data on the entire data
bus will appear in subsequent successive Read cycles after an interval of 1 µs. During internal Erase
operation, any attempt to read DQ
7
will produce a ‘0’. Once the internal Erase operation is completed,
DQ
7
will produce a ‘1’. Proper status will not be given using Data# Polling if the address is in the invalid
range.
Toggle Bit (DQ
6
)
During the internal Program or Erase operation, any consecutive attempts to read DQ
6
will produce
alternating ‘0’s and ‘1’s, i.e., toggling between 0 and 1. When the internal Program or Erase operation
is completed, the toggling will stop.
Multiple Device Selection
The four ID pins, ID[3:0], allow multiple devices to be attached to the same bus by using different ID
strapping in a system. When the SST49LF008A is used as a boot device, ID[3:0] must be strapped as
0000, all subsequent devices should use a sequential up-count strapping (i.e. 0001, 0010, 0011, etc.).
The SST49LF008A will compare the strapping values, if there is a mismatch, the device will ignore the
remainder of the cycle and go into standby mode. For further information regarding FWH device map-
