Si3453
Rev. 1.3 25
6. Operational Notes
6.1. Port Turn On
If the port is turned on by putting it in auto mode, the Si3453 will take care of all specified timing, and it will take
care of the two-event classification if the first event result is Class 4 and PoE+ mode is enabled. However, if
automatic mode operation is not desired after port turn-on, the port should be set to semi-auto or manual mode
once it has powered. In automatic mode, I
CUT
is set according to the classification result.
The port turn-on command is used to turn on a port in semi-auto or manual mode. If the port is turned on in semi-
auto mode, turn-on is delayed until the next detection and classification. If the detection or classification result is
not valid, the port will not power. If the classification is Class 4 and PoE+ mode is enabled, a 2-event classification
is given. I
CUT
setting is not automatic for port turn-on in semi-auto or manual mode.
If the port is turned on by putting it in manual mode, the normal sequence is to start with the port in semi-auto mode
and interrupt on a classification complete, which indicates that there is a valid PD signature and that a classification
result is available. Based on the classification result, the host can make a decision to apply power or not. The IEEE
standard requires that a port be powered within 400 ms of a valid detect complete. It is also desirable to power the
port prior to the start of the next detection pulse, which can occur in as little as 300 ms. Therefore, it is
recommended that ports be powered in under 250 ms from the class complete interrupt when using the manual
mode turn-on command.
Using manual mode turn-on, detection is not done prior to port turn on, but classification is always performed just
prior to port turn on. Ports are turned on in manual mode regardless of the classification result. 2-event
classification is performed if the first event result is Class 4 and the port is enabled for PoE+ mode. The manual
mode classification step does not generate a classification complete flag because it is assumed that the
classification was already done in semi-auto mode and the host has already made the decision to grant power.
During the initial 60 ms (Tstart) time of port turn-on, 1x current limit and I
CUT
= 375 mA (nominal) is enforced. After
Tstart, if the port is not overloaded, Pgood is set to true, and I
CUT
and 1x or 2x current limit will follow the I
2
C
register settings. In auto mode, the I
2
C registers are set according to the classification result, but, if desired, they
can be overwritten after Pgood becomes true. After Tstart, 2x current limit is always allowed if PoE+ mode is
enabled.
6.2. Changing the Interrupt Mask
The INT register and INT pin are always synchronized. However, there can be up to a 5 ms delay between an
event that causes or clears an interrupt and the update of the register and pin.
Thus, if the INT mask register is changed to clear an interrupt or to block an interrupt source, there can be up to a
5 ms delay between the change of the INT mask register and the resultant change in the INT register and INT
pin.
Generally, use of the mask register to clear interrupts is not recommended; it is better to clear an interrupt by
reading the appropriate COR register.
6.3. Port Voltage and Current Measurements
Port current voltage and current are reported as of the time the measurement command is written to register 0x12.
Spikes of current or other momentary current changes are not filtered. It may be desirable to add a ~1 second
averaging filter to reported current when using port current information for power management decisions.
Si3453
26 Rev. 1.3
7. PCB Layout Guidelines
Following are some PCB layout considerations. See also "12.1. Evaluation Kits and Reference Designs" on page
34 for reference design information. Please visit the Silicon Labs technical support web page at
www.silabs.com/support/pages/contacttechnicalsupport.aspx and register to request support for your design,
particularly if you are not closely following the recommended reference design.
Due to the high current of up to 800 mA per port, the following board layout guidelines apply. In addition, contact
Silicon Laboratories for access to complete PSE reference design databases including recommended layouts.
The VEE1, VEE2, VEE3, and VEE4 pins can carry up to 800 mA and are connected to a V
EE
bus. The V
EE
bus for
a 24 port PCB layout can thus carry as much as 20 A current. With 2 oz. copper on an outer layer, a bus of 0.4
inches is needed. For an inner layer, this increases to a 1 inch wide bus. Use of large or multiple vias is required for
properly supporting the 800 mA per channel operating current. The VEE pin does not carry high current and can be
connected directly to the bus as well. The best practice is to devote an entire inner layer for V
EE
power routing.
Similarly, GND1/2 and GND3/4 pins can carry up to 1.6 A per pin, and the GND return bus should be at least as
wide as the V
EE
bus described above. The best practice is to devote an entire inner layer for ground power routing.
The ground power plane does not generally have a high frequency content (other than external faults); so, it is
generally acceptable to use the ground power plane as a ground signal plane and tie AGND and GND12, GND34
to this plane as well.
The VOUTn pins carry up to 800 mA dc and up to 5 A in faults; so, a 20 mil trace with wide or multiple vias is also
recommended. The VDETn pins also carry fault current; so, this pin connection to VOUTn needs to use 20 mil
traces and wide or multiple vias where needed.
The VDD currents are not large; so, it is acceptable to route the VDD nodes on one of the outer layers.
If care is taken to avoid disruption of the high current paths, VDD can be globally routed on one of the power planes
and then locally routed on an inner or outer layer.
To avoid coupling between surge events and logic signals, it is recommended that VOUTn traces be routed on the
side opposite the I
2
C interface pins.
The thermal pad of the Si3453 is connected to VEE. At full IEEE 802.3at current of 600 mA on each port, the
dissipation of the Si3453 is up to 1.2 W; so, multiple vias are required to conduct the heat from the thermal pad to
the VEE plane. As many as 36 small vias provide the best thermal conduction.
Si3453
Rev. 1.3 27
8. Firmware Release Notes
Devices marked with firmware revision 02 (see "13. Device Marking Diagram" on page 35) have the firmware
revision registers set as 0x61 = 0x00; 0x62 = 0x02, and 0x63 = 0x51 (0.2.81).
The following is a known issue, which may be addressed with a future firmware revision:
8.1. I
2
C Address ACK
Issue: Very rarely, the Si3453 may not ACK the I
2
C address byte.
Impact: This is allowed in the I
2
C specification.
Workaround: Retransmit the address byte if there is an ACK failure.

SI3453B-B02-GM

Mfr. #:
Manufacturer:
Silicon Labs
Description:
Hot Swap Voltage Controllers
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