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SE97TK,118

P1-P3P4-P6P7-P9P10-P12P13-P15P16-P18P19-P21P22-P24P25-P27P28-P30P31-P33P34-P36P37-P39P40-P42P43-P45P46-P48P49-P51P52-P54P55-P55
SE97_7 © NXP B.V. 2010. All rights reserved.
Product data sheet Rev. 07 — 29 January 2010 19 of 55
NXP Semiconductors
SE97
DDR memory module temp sensor with integrated SPD, 3.3 V
Table 5 is the summary for normal and memory protection instructions.
[1] The most significant bit, bit 7, is sent first.
[2] A0, A1, and A2 are compared against the respective external pins on the SE97.
[3] V
I(ov)
ranges from 7.8 V to 10 V.
This special EEPROM command consists of a unique 4-bit fixed address (0110b) and the
voltage level applied on the 3-bit hardware address. Normally, to address the memory
array, the 4-bit fixed address is ‘1010b’. To access the memory protection settings, the
4-bit fixed address is ‘0110b’. Figure 17
and Figure 18 show the write and read protection
sequence, respectively.
Up to eight memory devices can be connected on a single I
2
C-bus. Each one is given a
3-bit on the hardware selectable address (A2, A1, A0) inputs. The device only responds
when the 4-bit fixed and hardware selectable bits are matched. The 8th bit is the
read/write bit. This bit is set to 1 or 0 for read and write protection, respectively.
The corresponding device acknowledges during the ninth bit time when there is a match
on the 7-bit address.
The device does not acknowledge when there is no match on the 7-bit address or when
the device is already in permanent write protection mode and is programmed with any
write protection instructions (i.e., PWP, RWP, CWP).
Table 5. EEPROM commands summary
Command Fixed address Hardware selectable
address
R/W
Bit 7
[1]
Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
Normal EEPROM read/write 1010A2A1A0R/W
Reversible Write Protection (RWP) 0110V
SS
V
SS
V
I(ov)
[3]
0
Clear Reversible Write Protection (CRWP)0110V
SS
V
DD
V
I(ov)
[3]
0
Permanent Write Protection (PWP)
[2]
0110A2A1A00
Read RWP 0110V
SS
V
SS
V
I(ov)
[3]
1
Read CRWP 0110V
SS
V
DD
V
I(ov)
[3]
1
Read PWP 0110A2A1A01
X = Don’t Care
(1) Refer to Table 6
regarding the exact state of the acknowledge bit.
Fig 17. Software Write Protect (write)
1 1 0 A2 A1 A0 0 AS 0 A
slave address (memory)
START condition R/W acknowledge
(1)
from slave
acknowledge
(1)
from slave
dummy byte address
SDA
dummy data
A
acknowledge
(1)
from slave
002aab356
P
STOP condition
XXXXXXXX
XXXXXXXX
SE97_7 © NXP B.V. 2010. All rights reserved.
Product data sheet Rev. 07 — 29 January 2010 20 of 55
NXP Semiconductors
SE97
DDR memory module temp sensor with integrated SPD, 3.3 V
7.10.2.1 Permanent Write Protection (PWP)
If the software write-protection has been set with the PWP instruction, the first 128 bytes
of the memory are permanently write-protected. This write-protection cannot be cleared
by any instruction, or by power-cycling the device. Also, once the PWP instruction has
been successfully executed, the device no longer acknowledges any instruction (with 4-bit
fixed address of 0110b) to access the write-protection settings.
7.10.2.2 Reversible Write Protection (RWP) and Clear Reversible Write Protection (CRWP)
If the software write-protection has been set with the RWP instruction, it can be cleared
again with a CRWP instruction.
The two instructions, RWP and CRWP have the same format as a Byte Write instruction,
but with a different setting for the hardware address pins (as shown in Table 5
). Like the
Byte Write instruction, it is followed by an address byte and a data byte, but in this case
the contents are all ‘Don’t Care’ (Figure 17
). Another difference is that the voltage, V
I(ov)
,
must be applied on the A0 pin, and specific logical levels must be applied on the other two
(A1 and A2), as shown in Table 5
.
X = Don’t Care
(1) Refer to Table 7
regarding the exact state of the acknowledge bit.
Fig 18. Software Write Protect (read)
1 1 0 A2 A1 A0 1 AS 0 A
slave address (memory)
START condition R/W acknowledge
(1)
from slave
no acknowledge
(1)
from slave
dummy byte address
SDA
dummy data
A
no acknowledge
(1)
from slave
002aac644
P
STOP condition
XXXXXXXX XXXXXXXX
Table 6. Acknowledge when writing data or defining write protection
Instructions with R/W
bit = 0.
Status Instruction ACK Address ACK Data byte ACK Write cycle
(T
cy(W)
)
Permanently
protected
PWP, RWP or CRWP NACK not significant NACK not significant NACK no
page or byte write in
lower 128 bytes
ACK address ACK data NACK no
Protected with
RWP
RWP NACK not significant NACK not significant NACK no
CRWP ACK not significant ACK not significant ACK yes
PWP ACK not significant ACK not significant ACK yes
page or byte write in
lower 128 bytes
ACK address ACK data NACK no
Not protected PWP or RWP ACK not significant ACK not significant ACK yes
CRWP ACK not significant ACK not significant ACK no
page or byte write ACK address ACK data ACK yes
SE97_7 © NXP B.V. 2010. All rights reserved.
Product data sheet Rev. 07 — 29 January 2010 21 of 55
NXP Semiconductors
SE97
DDR memory module temp sensor with integrated SPD, 3.3 V
7.10.2.3 Read Permanent Write Protection (RPWP), Read Reversible Write Protection
(RRWP), and Read Clear Reversible Write Protection (RCRWP)
Read PWP, RWP, and CRWP allow the SE97 to be read in write protection mode. The
instruction format is the same as that of the write protection except that the 8
th
bit, R/W, is
set to 1. Figure 18
shows the instruction format, while Table 7 shows the responses when
the instructions are issued.
7.10.3 Read operations
7.10.3.1 Current address read
In Standby mode, the SE97 internal address counter points to the data byte immediately
following the last byte accessed by a previous operation. If the ‘previous’ byte was the last
byte in memory, then the address counter will point to the first memory byte, and so on. If
the SE97 decodes a slave address with a ‘1’ in the R/W
bit position (Figure 19), it will
issue an Acknowledge in the ninth clock cycle and will then transmit the data byte being
pointed at by the address counter. The master can then stop further transmission by
issuing a No Acknowledge on the ninth bit then followed by a STOP condition.
7.10.3.2 Selective read
The read operation can also be started at an address different from the one stored in the
address counter. The address counter can be ‘initialized’ by performing a ‘dummy’ write
operation (Figure 20
). The START condition is followed by the slave address (with the
R/W
bit set to ‘0’) and the desired byte address. Instead of following-up with data, the
master then issues a second START, followed by the ‘Current Address Read’ sequence,
as described in Section 7.10.3.1
.
Table 7. Acknowledge when reading the write protection
Instructions with R/W bit = 1.
Status Instruction ACK Address ACK Data byte ACK
Permanently
protected
RPWP, RRWP or
RCRWP
NACK not significant NACK not significant NACK
Protected with
RWP
RRWP NACK not significant NACK not significant NACK
RCRWP ACK not significant NACK not significant NACK
RPWP ACK not significant NACK not significant NACK
Not protected RPWP, RRWP or
RCRWP
ACK not significant NACK not significant NACK
Fig 19. Current address read timing
0 1 0 A2 A1 A0 1 AS 1
slave address (memory)
START condition R/W acknowledge
from slave
data from memory
SDA
002aab251
P
STOP condition
no acknowledge
from master
A
P1-P3P4-P6P7-P9P10-P12P13-P15P16-P18P19-P21P22-P24P25-P27P28-P30P31-P33P34-P36P37-P39P40-P42P43-P45P46-P48P49-P51P52-P54P55-P55

SE97TK,118

Mfr. #:
Buy SE97TK,118
Manufacturer:
NXP Semiconductors
Description:
IC TEMP SENSOR DIMM 8-HVSON
Lifecycle:
New from this manufacturer.
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