SE97_7 © NXP B.V. 2010. All rights reserved.
Product data sheet Rev. 07 — 29 January 2010 7 of 55
NXP Semiconductors
SE97
DDR memory module temp sensor with integrated SPD, 3.3 V
7. Functional description
7.1 Serial bus interface
The SE97 communicates with a host controller by means of the 2-wire serial bus
(I
2
C-bus/SMBus) that consists of a serial clock (SCL) and serial data (SDA) signals. The
device supports SMBus, I
2
C-bus Standard-mode and Fast-mode. The I
2
C-bus standard
speed is defined to have bus speeds from 0 Hz to 100 kHz, I
2
C-bus fast speed from 0 Hz
to 400 kHz, and the SMBus is from 10 kHz to 100 kHz. The host or bus master generates
the SCL signal, and the SE97 uses the SCL signal to receive or send data on the SDA
line. Data transfer is serial, bidirectional, and is one byte at a time with the Most Significant
Bit (MSB) is transferred first. Since SCL and SDA are open-drain, pull-up resistors must
be installed on these pins.
7.2 Slave address
The SE97 uses a 4-bit fixed and 3-bit programmable (A0, A1 and A2) 7-bit slave address
that allows a total of eight devices to coexist on the same bus. The A0, A1 and A2 pins are
pulled LOW internally. The A0 pin is also overvoltage tolerant supporting 10 V software
write protect. When it is driven higher than 7.8 V, writing a special command would put the
EEPROM in reversible write protect mode (see Section 7.10.2 “
Memory protection). Each
pin is sampled at the start of each I
2
C-bus/SMBus access. The temperature sensor’s fixed
address is ‘0011b’. The EEPROM’s fixed address for the normal EEPROM read/write is
‘1010b’, and for EEPROM software protection command is ‘0110b’. Refer to Figure 7
.
a. Temperature sensor b. EEPROM (normal read/write) c. EEPROM (software
protection command)
Fig 7. Slave address
R/W
002aab30
4
0 0 1 1 A2 A1 A0
fixed hardware
selectable
slave address
MSB LSB
X
R/W
002aab35
1
1 0 1 0 A2 A1 A0
fixed hardware
selectable
slave address
MSB LSB
X
R/W
002aab35
2
0 1 1 0 A2 A1 A0
fixed hardware
selectable
slave address
MSB LSB
X
SE97_7 © NXP B.V. 2010. All rights reserved.
Product data sheet Rev. 07 — 29 January 2010 8 of 55
NXP Semiconductors
SE97
DDR memory module temp sensor with integrated SPD, 3.3 V
7.3 EVENT output condition
The EVENT output indicates conditions such as the temperature crossing a predefined
boundary. The EVENT
modes are very configurable and selected using the configuration
register (CONFIG). The interrupt mode or comparator mode is selected using CONFIG[0],
using either TCRIT/UPPER/LOWER or TCRIT only temperature bands (CONFIG[2]) as
modified by hysteresis (CONFIG[10:9]). The UPPER/LOWER (CONFIG[6]) and TCRIT
(CONFIG[7]) bands can be locked. Figure 8
shows an example of the measured
temperature versus time, with the corresponding behavior of the EVENT
output in each of
these modes.
Upon device power-up, the default condition for the EVENT
output is high-impedance to
prevent spurious or unwanted alarms, but can be later enabled (CONFIG[3]). EVENT
output polarity can be set to active HIGH or active LOW (CONFIG[1]). EVENT
status can
be read (CONFIG[4]) and cleared (CONFIG[5]).
Advisory note:
NXP device: After power-up, bit 3 (1) and bit 2 or bit 0 (leave as 0 or 1) can be set
at the same time (e.g., in same byte) but once bit 3 is set (1) then changing bit 2 or
bit 0 has no effect on the device operation.
Competitor device: Does not require that bit 3 be cleared (e.g., set back to (0))
before changing bit 2 or bit 0.
Work-around: In order to change bit 2 or bit 0 once bit 3 (1) is set, bit 3 (0) must be
cleared in one byte and then change bit 2 or bit 0 and reset bit 3 (1) in the next
byte.
SE97B will allow bit 2 or bit 0 to be changed even if bit 3 is set.
If the device enters Shutdown mode (CONFIG[8]) with asserted EVENT
output, the output
remains asserted during shutdown.
7.3.1 EVENT pin output voltage levels and resistor sizing
The EVENT open-drain output is typically pulled up to a voltage level from 0.9 V to 3.6 V
with an external pull-up resistor, but there is no real lower limit on the pull-up voltage for
the EVENT
pin since it is simply an open-drain output. It could be pulled up to 0.1 V and
would not affect the output. From the system perspective, there will be a practical limit.
That limit will be the voltage necessary for the device monitoring the interrupt pin to detect
a HIGH on its input. A possible practical limit for a CMOS input would be 0.4 V. Another
thing to consider is the value of the pull-up resistor. When a low supply voltage is applied
to the drain (through the pull-up resistor) it is important to use a higher value pull-up
resistor, to allow a larger maximum signal swing on the EVENT
pin.
SE97_7 © NXP B.V. 2010. All rights reserved.
Product data sheet Rev. 07 — 29 January 2010 9 of 55
NXP Semiconductors
SE97
DDR memory module temp sensor with integrated SPD, 3.3 V
When T
amb
T
th(crit)
and T
amb
< T
th(crit)
T
hys
the EVENT output is in Comparator mode
and bit 0 of CONFIG (EVENT
output mode) is ignored.
Refer to Table 3 for figure note information.
Fig 8. EVENT output condition
002aae324
time
temperature (°C)
critical
EVENT in Interrupt mode
EVENT in Comparator mode
software interrupt clear
Lower Boundary Alarm
Upper Boundary Alarm
EVENT in ‘Critical Temp only’ mode
(1) (2) (1) (3) (4) (3)(5) * (6) (4) (2)
T
amb
T
trip(l)
T
hys
T
trip(u)
T
hys
T
th(crit)
T
hys
T
trip(u)
T
hys
T
trip(l)
T
hys
Table 3. EVENT output condition
Figure
note
EVENT output boundary
conditions
EVENT output Temperature Register Status bits
Comparator
mode
Interrupt
mode
Critical Temp
only mode
Bit 15
Above
Critical
Trip
Bit 14
Above
Alarm
Window
Bit 13
Below
Alarm
Window
(1) T
amb
T
trip(l)
HLH000
(2) T
amb
< T
trip(l)
T
hys
LLH001
(3) T
amb
> T
trip(u)
LLH010
(4) T
amb
T
trip(u)
T
hys
HLH000
(5) T
amb
T
th(crit)
LLL110
(6) T
amb
< T
th(crit)
T
hys
LHH010

SE97TK,118

Mfr. #:
Manufacturer:
NXP Semiconductors
Description:
IC TEMP SENSOR DIMM 8-HVSON
Lifecycle:
New from this manufacturer.
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