SE97_7 © NXP B.V. 2010. All rights reserved.
Product data sheet Rev. 07 — 29 January 2010 43 of 55
NXP Semiconductors
SE97
DDR memory module temp sensor with integrated SPD, 3.3 V
[1] Minimum clock frequency is 0 kHz if SMBus Time-out is disabled.
[2] Delay from SDA STOP to SDA START.
[3] A device must internally provide a hold time of at least 200 ns for SDA signal (referenced to the V
IH(min)
of the SCL signal) to bridge the
undefined region of the falling edge of SCL.
[4] Delay from SCL HIGH-to-LOW transition to SDA edges.
[5] Delay from SCL LOW-to-HIGH transition to restart SDA.
[6] Delay from SDA START to first SCL HIGH-to-LOW transition.
[7] These parameters tested initially and after a design or process change that affects the parameter.
[8] t
pu(R)
and t
pu(W)
are the delays required from the time V
DD
is stable until the specified operation can be initiated.
Table 30. SMBus AC characteristics
V
DD
= 1.7 V to 3.6 V; T
amb
=
−
40
°
C to +125
°
C; unless otherwise specified. These specifications are guaranteed by design.
The AC specifications fully meet or exceed SMBus 2.0 specifications, but allow the bus to interface with the I
2
C-bus from DC
to 400 kHz.
Symbol Parameter Conditions Standard mode Fast mode Unit
Min Max Min Max
f
SCL
SCL clock frequency 10
[1]
100 10
[1]
400 kHz
t
HIGH
HIGH period of the SCL clock 70 % to 70 % 4000 - 600 - ns
t
LOW
LOW period of the SCL clock 30 % to 30 % 4700 - 1300 - ns
t
to(SMBus)
SMBus time-out time LOW period to reset
SMBus
25 35 25 35 ms
t
r
rise time of both SDA and
SCL signals
- 1000 20 300 ns
t
f
fall time of both SDA and SCL
signals
- 300 - 300 ns
t
SU;DAT
data set-up time 250 - 100 - ns
t
h(i)(D)
data input hold time
[2][3]
0-0-ns
t
HD;DAT
data hold time
[4]
200 3450 200 900 ns
t
SU;STA
set-up time for a repeated
START condition
[5]
4700 - 600 - ns
t
HD;STA
hold time (repeated) START
condition
30 % of SDA to
70 % of SCL
[6]
4000 - 600 - ns
t
SU;STO
set-up time for STOP
condition
4000 - 600 - ns
t
BUF
bus free time between a
STOP and START condition
[2]
4700 - 1300 - ns
t
SP
pulse width of spikes that
must be suppressed by the
input filter
-50-50ns
t
VD;DAT
data valid time from clock 200 - 200 - ns
t
f(o)
output fall time - - - 250 ns
t
POR
power-on reset pulse time power supply falling 0.5 - 0.5 - μs
EEPROM power-up timing
[7]
t
pu(R)
read power-up time
[8]
-1-1ms
t
pu(W)
write power-up time
[8]
-1-1ms
Write cycle limits
T
cy(W)
write cycle time
[9]
-10-10ms
