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SE97TK,118

P1-P3P4-P6P7-P9P10-P12P13-P15P16-P18P19-P21P22-P24P25-P27P28-P30P31-P33P34-P36P37-P39P40-P42P43-P45P46-P48P49-P51P52-P54P55-P55
SE97_7 © NXP B.V. 2010. All rights reserved.
Product data sheet Rev. 07 — 29 January 2010 25 of 55
NXP Semiconductors
SE97
DDR memory module temp sensor with integrated SPD, 3.3 V
8.3 Configuration register (01h, 16-bit read/write)
Table 11. Configuration register (address 01h) bit allocation
Bit 15 14 13 12 11 10 9 8
Symbol RFU HEN SHMD
Default 00000000
Access RRRRRR/WR/WR/W
Bit 7 6 5 4 3 2 1 0
Symbol CTLB AWLB CEVNT ESTAT EOCTL CVO EP EMD
Default 00000000
Access R/W R/W R/W R/W R/W R/W R/W R/W
Table 12. Configuration register (address 01h) bit description
Bit Symbol Description
15:11 RFU reserved for future use; must be ‘0’.
10:9 HEN Hysteresis Enable.
00 — disable hysteresis (default)
01 — enable hysteresis at 1.5 °C
10 — enable hysteresis at 3 °C
11 — enable hysteresis at 6 °C
When enabled, hysteresis is applied to temperature movement around trigger
points. For example, consider the behavior of the ‘Above Alarm Window’ bit
(bit 14 of the Temperature register) when the hysteresis is set to 3 °C. As the
temperature rises, bit 14 will be set to ‘1’ (temperature is above the alarm
window) when the Temperature register contains a value that is greater than the
value in the Alarm Temperature Upper Boundary register. If the temperature
decreases, bit 14 will remain set until the measured temperature is less than or
equal to the value in the Alarm Temperature Upper Boundary register minus
3 °C. (Refer to Figure 8
and Table 13).
Similarly, the ‘Below Alarm Window’ bit (bit 13 of the Temperature register) will
be set to ‘0’ (temperature is equal to or above the Alarm Window Lower
Boundary Trip register) when the value in the Temperature register is equal to or
greater than the value in the Alarm Temperature Lower Boundary register. As
the temperature decreases, bit 13 will be set to ‘1’ when the value in the
Temperature register is equal to or less than the value in the Alarm Temperature
Lower Boundary register minus 3 °C. Note that hysteresis is also applied to
EVENT
pin functionality.
When either of the Critical Trip or Alarm Window lock bits is set, these bits
cannot be altered until unlocked.
SE97_7 © NXP B.V. 2010. All rights reserved.
Product data sheet Rev. 07 — 29 January 2010 26 of 55
NXP Semiconductors
SE97
DDR memory module temp sensor with integrated SPD, 3.3 V
8 SHMD Shutdown Mode.
0 — enabled Temperature Sensor (default)
1 — disabled Temperature Sensor
When shut down, the thermal sensor diode and ADC are disabled to save
power, no events will be generated. When either of the Critical Trip or Alarm
Window lock bits is set, this bit cannot be set until unlocked. However, it can be
cleared at any time.
Remark: SMBus Time-out works over the entire supply range of 1.7 V to 3.6 V
unless the shutdown bit (SHMD) is set and turns off the oscillator.
• The EEPROM read works over the entire supply range of 1.7 V to 3.6 V
whether or not SHMD is set because it does not need oscillator to function.
There is no undervoltage lockout, the device no longer responds at some
voltage below 1.7 V.
• EEPROM write works over the supply range of 3.0 V to 3.6 V, but not if
SHMD is set since the oscillator is needed to write to EEPROM. There is an
undervoltage lockout around 2.7 V that disables the RRPROM write
operation.
• Thermal sensor is operational over the supply range of 3.0 V to 3.6 V, but
not if SHMD is set since the oscillator is needed. There is an undervoltage
lockout around 2.7 V that disables the temp sensor.
Thermal sensor auto turn-off feature:
It was determined during testing of the SE97TP on 5 May 2008 that the Thermal
Sensor auto turn-off feature was not compatible with the JEDEC power supply
maximum ramp rate of 70 ms to 100 ms (slowest ramp rate) and this feature was
disabled for all SE97 samples/production devices tested after 6 May (wk 0818
date code is when the devices were assembled).
If there is a slow ramp rate on the supply voltage to 3.3 V the SE97 would be EE
read only and not Thermal Sensor. This is due to a feature integrated into the
device to automatically turn off the oscillator and place the thermal sensor in
shutdown if the SE97 was being used in SO-DIMM in notebook applications at
1.8 V to reduce the power consumption on the battery. The feature counts for
30 ms (± 5 ms) after the oscillator starts working (around 1.2 V to 1.7 V) and if at
30 ms the voltage is greater than 2.4 V, the oscillator is left on and the Thermal
Sensor functions as normal. But if the voltage is less than 2.4 V at 30 ms, the
oscillator is turned off and the SE97 will think the part is in SPD only mode
defaulting to the oscillator and Thermal Sensor disabled (SHMD Shutdown
Mode bit 8 = 1). The oscillator and Thermal Sensor can be re-enabled by writing
a logic 0 to SHMD. It is important in RDIMM/server applications that the Thermal
Sensor is working as the default condition since the Thermal Sensor needs to be
compatible with the JEDEC power supply ramp rate (maximum ramp rate is
70 ms to 100 ms) so the Thermal Sensor auto turn-off feature was disabled
starting on 6 May 2008 by changing a programmable bit on the device during
final test. There is no change in performance of the SE97 with this feature turned
off and was verified during characterization. There is no way to read the SE97
registers via the I
2
C-bus to determine if the Thermal Sensor auto turn-off feature
is enabled or disabled. This is set in a factory only register. You need to check
the date code or do an operational test (e.g., run up to < 2.4 V, hold, then go to
3.3 V, then read SHMD bit 8 in the Configuration register to see if it is set to
logic 0 (e.g., oscillator running = feature disabled) or logic 1 (e.g., oscillator
turned off = feature enabled)). The Thermal Sensor auto turn-off feature is active
in all package options prior to wk 0818. The SE97TP and SE97TL were not yet
released to production so there is a clear line at release/orderable devices
versus samples with this feature disabled in all production devices.
Table 12. Configuration register (address 01h) bit description
…continued
Bit Symbol Description
SE97_7 © NXP B.V. 2010. All rights reserved.
Product data sheet Rev. 07 — 29 January 2010 27 of 55
NXP Semiconductors
SE97
DDR memory module temp sensor with integrated SPD, 3.3 V
7 CTLB Critical Trip Lock bit.
0 — Critical Alarm Trip register is not locked and can be altered (default)
1 — Critical Alarm Trip register settings cannot be altered
This bit is initially cleared. When set, this bit will return a ‘1’, and remains locked
until cleared by internal Power-on reset. This bit can be written with a single
write and do not require double writes.
6 AWLB Alarm Window Lock bit.
0 — Upper and Lower Alarm Trip registers are not locked and can be altered
(default)
1 — Upper and Lower Alarm Trip registers setting cannot be altered
This bit is initially cleared. When set, this bit will return a ‘1’ and remains locked
until cleared by internal power-on reset. This bit can be written with a single write
and does not require double writes.
5 CEVNT Clear EVENT (write only).
0 — no effect (default)
1 — clears active EVENT
in Interrupt mode. Writing to this register has no
effect in Comparator mode.
When read, this register always returns zero.
4 ESTAT EVENT Status (read only).
0 — EVENT output condition is not being asserted by this device (default)
1 — EVENT
output pin is being asserted by this device due to Alarm Window
or Critical Trip condition
The actual event causing the EVENT can be determined from the Read
Temperature register. Interrupt Events can be cleared by writing to the ‘Clear
EVENT
’ bit (CEVNT). Writing to this bit will have no effect.
3 EOCTL EVENT
Output Control.
0 — EVENT
output disabled (default)
1 — EVENT
output enabled
When either of the Critical Trip or Alarm Window lock bits is set, this bit cannot
be altered until unlocked.
2 CVO Critical Event Only.
0 — EVENT
output on Alarm or Critical temperature event (default)
1 — EVENT only if temperature is above the value in the critical temperature
register
When the Critical Trip or Alarm Window lock bit is set, this bit cannot be altered
until unlocked.
• Advisory note:
– JEDEC specification requires only the Alarm Window lock bit to be set.
– Work-around: Clear both Critical Trip and Alarm Window lock bits.
– Future 1.7 V to 3.6 V SE97B will require only the Alarm Window lock bit
to be set.
1 EP EVENT
Polarity.
0 — active LOW (default)
1 — active HIGH. When either of the Critical Trip or Alarm Window lock bits is
set, this bit cannot be altered until unlocked.
Table 12. Configuration register (address 01h) bit description
…continued
Bit Symbol Description
P1-P3P4-P6P7-P9P10-P12P13-P15P16-P18P19-P21P22-P24P25-P27P28-P30P31-P33P34-P36P37-P39P40-P42P43-P45P46-P48P49-P51P52-P54P55-P55

SE97TK,118

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Buy SE97TK,118
Manufacturer:
NXP Semiconductors
Description:
IC TEMP SENSOR DIMM 8-HVSON
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New from this manufacturer.
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