Freescale Semiconductor
Technical Data
© 2011 Freescale Semiconductor, Inc. All rights reserved.
This document provides an overview of the MPC8306S
PowerQUICC II Pro processor features. The MPC8306S is
a cost-effective, highly integrated communications
processor that addresses the requirements of several
networking applications, including residential gateways,
modem/routers, industrial control, and test and measurement
applications. The MPC8306S extends current PowerQUICC
offerings, adding higher CPU performance, additional
functionality, and faster interfaces, while addressing the
requirements related to time-to-market, price, power
consumption, and board real estate. This document describes
the electrical characteristics of MPC8306S.
To locate published errata or updates for this document, refer
to the MPC8306S product summary page on our website
listed on the back cover of this document or contact your
local Freescale sales office.
Document Number: MPC8306SEC
Rev. 1, 09/2011
Contents
1. Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2
2. Electrical Characteristics . . . . . . . . . . . . . . . . . . . . . . 6
3. Power Characteristics . . . . . . . . . . . . . . . . . . . . . . . . 10
4. Clock Input Timing . . . . . . . . . . . . . . . . . . . . . . . . . . 11
5. RESET Initialization . . . . . . . . . . . . . . . . . . . . . . . . . 12
6. DDR2 SDRAM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
7. Local Bus . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
8. Ethernet and MII Management . . . . . . . . . . . . . . . . . 21
9. TDM/SI . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28
10. HDLC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29
11. USB . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31
12. DUART . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33
13. I
2
C . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34
14. Timers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36
15. GPIO . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37
16. IPIC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38
17. SPI . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38
18. JTAG . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40
19. Package and Pin Listings . . . . . . . . . . . . . . . . . . . . . 44
20. Clocking . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 54
21. Thermal . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 61
22. System Design Information . . . . . . . . . . . . . . . . . . . 64
23. Ordering Information . . . . . . . . . . . . . . . . . . . . . . . . 67
24. Document Revision History . . . . . . . . . . . . . . . . . . . 69
MPC8306S
PowerQUICC II Pro Integrated
Communications Processor
Family Hardware Specifications
MPC8306S PowerQUICC II Pro Integrated Communications Processor Family Hardware Specifications, Rev. 1
2 Freescale Semiconductor
Overview
1 Overview
The MPC8306S incorporates the e300c3 (MPC603e-based) core built on Power Architecture®
technology, which includes 16 Kbytes of each L1 instruction and data caches, dual integer units, and
on-chip memory management units (MMUs). The MPC8306S also includes two DMA engines and a
16-bit DDR2 memory controller.
A new communications complex based on QUICC Engine technology forms the heart of the networking
capability of the MPC8306S. The QUICC Engine block contains several peripheral controllers and a
32-bit RISC controller. Protocol support is provided by the main workhorses of the device—the unified
communication controllers (UCCs). A block diagram of the MPC8306S is shown in the following figure.
Figure 1. MPC8306S Block Diagram
Each of the five UCCs can support a variety of communication protocols such as 10/100 Mbps MII/RMII
Ethernet, HDLC and TDM.
3 RMII/MII
2x TDM Ports
16-KB
D-Cache
16-KB
I-Cache
e300c3 Core with Power
2 x DUART
Interrupt
I2C
Timers
GPIO
DDR2
Controller
Controller
Baud Rate
Generators
Accelerators
Single 32-bit RISC CP
Serial DMA
Serial Interface
QUICC Engine™ Block
UCC7
UCC5
UCC3
UCC2
UCC1
Time Slot Assigner
16 KB Multi-User RAM
FPU
Management
SPI
RTC
2x HDLC
DMA
48 KB Instruction RAM
Engine
USB 2.0 HS
Host/Device/OTG
ULPI
Enhanced Local
Bus Controller
MPC8306S PowerQUICC II Pro Integrated Communications Processor Family Hardware Specifications, Rev. 1
Freescale Semiconductor 3
Overview
In summary, the MPC8306S provides users with a highly integrated, fully programmable communications
processor. This helps to ensure that a low-cost system solution can be quickly developed and offers
flexibility to accommodate new standards and evolving system requirements.
1.1 Features
The major features of the device are as follows:
e300c3 Power Architecture processor core
Enhanced version of the MPC603e core
High-performance, superscalar processor core with a four-stage pipeline and low interrupt
latency times
Floating-point, dual integer units, load/store, system register, and branch processing units
16-Kbyte instruction cache and 16-Kbyte data cache with lockable capabilities
Dynamic power management
Enhanced hardware program debug features
Software-compatible with Freescale processor families implementing Power Architecture
technology
Separate PLL that is clocked by the system bus clock
Performance monitor
QUICC Engine block
32-bit RISC controller for flexible support of the communications peripherals with the
following features:
One clock per instruction
Separate PLL for operating frequency that is independent of system’s bus and e300 core
frequency for power and performance optimization
32-bit instruction object code
Executes code from internal IRAM
32-bit arithmetic logic unit (ALU) data path
Modular architecture allowing for easy functional enhancements
Slave bus for CPU access of registers and multiuser RAM space
48 Kbytes of instruction RAM
16 Kbytes of multiuser data RAM
Serial DMA channel for receive and transmit on all serial channels
Five unified communication controllers (UCCs) supporting the following protocols and
interfaces:
10/100 Mbps Ethernet/IEEE Std. 802.3® through MII and RMII interfaces.
HDLC/Transparent (bit rate up to QUICC Engine operating frequency / 8)
HDLC Bus (bit rate up to 10 Mbps)
Asynchronous HDLC (bit rate up to 2 Mbps)

MPC8306SCVMABDCA

Mfr. #:
Manufacturer:
NXP / Freescale
Description:
Microprocessors - MPU E300 MP ext tmp 133
Lifecycle:
New from this manufacturer.
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