MPC8306S PowerQUICC II Pro Integrated Communications Processor Family Hardware Specifications, Rev. 1
Freescale Semiconductor 67
Ordering Information
The following table summarizes the signal impedance targets. The driver impedance is targeted at
minimum V
DD
, nominal OV
DD
, 105C.
22.5 Configuration Pin Multiplexing
The MPC8306S provides the user with power-on configuration options which can be set through the use
of external pull-up or pull-down resistors of 4.7 k on certain output pins (Refer to the “Reset, Clocking
and Initialization” of MPC8306S PowerQUICC II Pro Integrated Communications Processor Family
Reference Manual). These pins are generally used as output only pins in normal operation.
While HRESET is asserted however, these pins are treated as inputs. The value presented on these pins
while HRESET is asserted, is latched when HRESET deasserts, at which time the input receiver is disabled
and the I/O circuit takes on its normal function. Careful board layout with stubless connections to these
pull-up/pull-down resistors coupled with the large value of the pull-up/pull-down resistor should minimize
the disruption of signal quality or speed for output pins thus configured.
23 Ordering Information
This section presents ordering information for the devices discussed in this document, and it shows an
example of how the parts are marked. Ordering information for the devices fully covered by this document
is provided in Section 23.1, “Part Numbers Fully Addressed by This Document.”
23.1 Part Numbers Fully Addressed by This Document
The following table provides the Freescale part numbering nomenclature for the MPC8306S family. Note
that the individual part numbers correspond to a maximum processor core frequency. For available
frequencies, contact your local Freescale sales office. In addition to the maximum processor core
frequency, the part numbering scheme also includes the maximum effective DDR memory speed and
QUICC Engine bus frequency. Each part number also contains a revision code which refers to the die mask
revision number.
Table 56. Impedance Characteristics
Impedance
Local Bus, Ethernet, DUART, Control,
Configuration and Power Management
DDR DRAM Symbol Unit
R
N
42 Target 20 Target Z
0
Ω
R
P
42 Target 20 Target Z
0
Ω
Differential NA NA Z
DIFF
Ω
Note: Nominal supply voltages. See Table 1, T
j
= 105C.
