MPC8306S PowerQUICC II Pro Integrated Communications Processor Family Hardware Specifications, Rev. 1
52 Freescale Semiconductor
Package and Pin Listings
FEC3_TXD0/TSEC_TMR_PP2/GPIO[60] R20 IO OV
DD
—
FEC3_TXD1/TSEC_TMR_PP3/GPIO[61] T22 IO OV
DD
—
FEC3_TXD2/TSEC_TMR_ALARM1/GPIO[62] T23 IO OV
DD
—
FEC3_TXD3/TSEC_TMR_ALARM2/GPIO[63] T20 IO OV
DD
—
HDLC/GPIO/TDM
HDLC1_RXCLK/TDM1_RCK/GPIO[1] U23 IO OV
DD
—
HDLC1_RXD/TDM1_RD/GPIO[3] U22 IO OV
DD
—
HDLC1_TXCLK/GPIO[0]/TDM1_TCK/
QE_BRG[5]
AC22 IO OV
DD
—
HDLC1_TXD/GPIO[2]/TDM1_TD/
CFG_RESET_SOURCE[0]
W18 IO OV
DD
—
HDLC1_CD_B/GPIO[4]/TDM1_TFS W19 IO OV
DD
—
HDLC1_CTS_B/GPIO[5]/TDM1_RFS Y20 IO OV
DD
—
HDLC1_RTS_B/GPIO[6]/TDM1_STROBE_B/
CFG_RESET_SOURCE[1]
AB22 IO OV
DD
—
HDLC2_TXCLK/GPIO[16]/TDM2_TCK/
QE_BRG[7]
AB23 IO OV
DD
—
HDLC2_RXCLK/GPIO[17]/TDM2_RCK/
QE_BRG[8]
AA23 IO OV
DD
—
HDLC2_TXD/GPIO[18]/TDM2_TD/
CFG_RESET_SOURCE[2]
W20 IO OV
DD
—
HDLC2_RXD/GPIO[19]/TDM2_RD Y23 IO OV
DD
—
HDLC2_CD_B/GPIO[20]/TDM2_TFS Y22 IO OV
DD
—
HDLC2_CTS_B/GPIO[21]/TDM2_RFS W23 IO OV
DD
—
HDLC2_RTS_B/GPIO[22]/TDM2_STROBE_B/
CFG_RESET_SOURCE[3]
W22 IO OV
DD
—
Power
AV
DD1
L16 — — —
AV
DD2
M16 — — —
AV
DD3
N8 — — —
GV
DD
G5, H5, J5, K5, L5, M5,
N5, P5, R5, T5, U5
———
OV
DD
E7,E8,E9,E10,E11,E12,
E13,E14, E15,
E16,E17,G19,H19,J19,K
19,L19,M19,
N19,P19,R19,T19,U19,
W7,W8,W9, W10,W11,
W12,W13, W14,W15,
W16, W17
———
Table 46. MPC8306S Pinout Listing (continued)
Signal Package Pin Number Pin Type Power Supply Notes