MPC8306S PowerQUICC II Pro Integrated Communications Processor Family Hardware Specifications, Rev. 1
52 Freescale Semiconductor
Package and Pin Listings
FEC3_TXD0/TSEC_TMR_PP2/GPIO[60] R20 IO OV
DD
FEC3_TXD1/TSEC_TMR_PP3/GPIO[61] T22 IO OV
DD
FEC3_TXD2/TSEC_TMR_ALARM1/GPIO[62] T23 IO OV
DD
FEC3_TXD3/TSEC_TMR_ALARM2/GPIO[63] T20 IO OV
DD
HDLC/GPIO/TDM
HDLC1_RXCLK/TDM1_RCK/GPIO[1] U23 IO OV
DD
HDLC1_RXD/TDM1_RD/GPIO[3] U22 IO OV
DD
HDLC1_TXCLK/GPIO[0]/TDM1_TCK/
QE_BRG[5]
AC22 IO OV
DD
HDLC1_TXD/GPIO[2]/TDM1_TD/
CFG_RESET_SOURCE[0]
W18 IO OV
DD
HDLC1_CD_B/GPIO[4]/TDM1_TFS W19 IO OV
DD
HDLC1_CTS_B/GPIO[5]/TDM1_RFS Y20 IO OV
DD
HDLC1_RTS_B/GPIO[6]/TDM1_STROBE_B/
CFG_RESET_SOURCE[1]
AB22 IO OV
DD
HDLC2_TXCLK/GPIO[16]/TDM2_TCK/
QE_BRG[7]
AB23 IO OV
DD
HDLC2_RXCLK/GPIO[17]/TDM2_RCK/
QE_BRG[8]
AA23 IO OV
DD
HDLC2_TXD/GPIO[18]/TDM2_TD/
CFG_RESET_SOURCE[2]
W20 IO OV
DD
HDLC2_RXD/GPIO[19]/TDM2_RD Y23 IO OV
DD
HDLC2_CD_B/GPIO[20]/TDM2_TFS Y22 IO OV
DD
HDLC2_CTS_B/GPIO[21]/TDM2_RFS W23 IO OV
DD
HDLC2_RTS_B/GPIO[22]/TDM2_STROBE_B/
CFG_RESET_SOURCE[3]
W22 IO OV
DD
Power
AV
DD1
L16
AV
DD2
M16
AV
DD3
N8
GV
DD
G5, H5, J5, K5, L5, M5,
N5, P5, R5, T5, U5
——
OV
DD
E7,E8,E9,E10,E11,E12,
E13,E14, E15,
E16,E17,G19,H19,J19,K
19,L19,M19,
N19,P19,R19,T19,U19,
W7,W8,W9, W10,W11,
W12,W13, W14,W15,
W16, W17
——
Table 46. MPC8306S Pinout Listing (continued)
Signal Package Pin Number Pin Type Power Supply Notes
MPC8306S PowerQUICC II Pro Integrated Communications Processor Family Hardware Specifications, Rev. 1
Freescale Semiconductor 53
Package and Pin Listings
V
DD
H8,H9,H10,H11,H12,H1
3,H14,H15,H16,J8,J16,K
8,K16,M8,N16,P8,P16,R
8,R16,T8,T9,T10,T11,T1
2,T13,T14,T15,T16
——
VSS A1,B4,B6,B9,B12,B15,B
18,B21,C22,D2,D5,D18,
D20,F2,F22,J2,J9,J10,J
11,J12,J13,J14,J15,J22,
K4,K9,K10,K11,K12,K13
,K14,K15,L9,L10,L11,L1
2,L13,L14,L15,M2,M9,M
10,M11,M12,M13,M14,M
15,M22,N9,N10,N11,N1
2,N13,N14,N15,P9,P10,
P11,P12,P13,P14,P15,R
2,R9,R10,R11,R12,R13,
R14,R15,R22,T4,V2,V19
,V22,W4,Y19,AA2,AA22,
AB4,AB6,AB9,AB12,AB1
5,AB18,AB21,AC1,AC23
——
NC A23
Notes
1. This pin is an open drain signal. A weak pull-up resistor (1 k) should be placed on this pin to OV
DD
2. This pin is an open drain signal. A weak pull-up resistor (2-10 k) should be placed on this pin to OV
DD
3. This pin has weak pull-up that is always enabled.
Table 46. MPC8306S Pinout Listing (continued)
Signal Package Pin Number Pin Type Power Supply Notes
MPC8306S PowerQUICC II Pro Integrated Communications Processor Family Hardware Specifications, Rev. 1
54 Freescale Semiconductor
Clocking
20 Clocking
The following figure Figure 39 shows the internal distribution of clocks within the MPC8306S.
Figure 38. MPC8306S Clock Subsystem
Figure 39. MPC8306S Clock Subsystem
The primary clock source for MPC8306S is SYS_CLK_IN.
Figure 40.
Core PLL
System
LBC
LCLK[0:1]
core_clk
e300c3 core
csb_clk to rest
csb_clk
Local Bus
Clock
Unit
of the device
lbc_clk
QE PLL
Memory
Device
/n
to local bus
Clock
MEMC_MCK
MEMC_MCK
DDR
ddr_clk
DDR
Memory
Device
PLL
to DDR
memory
controller
Clock
/2
Divider
Divider
qe_clk
MPC8306S
CLK Gen
QE_CLK_IN
QE Block
SYS_CLK_IN

MPC8306SCVMABDCA

Mfr. #:
Manufacturer:
NXP / Freescale
Description:
Microprocessors - MPU E300 MP ext tmp 133
Lifecycle:
New from this manufacturer.
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