MPC8306S PowerQUICC II Pro Integrated Communications Processor Family Hardware Specifications, Rev. 1
Freescale Semiconductor 25
Ethernet and MII Management
The following figure shows the RMII transmit AC timing diagram.
Figure 15. RMII Transmit AC Timing Diagram
8.2.2.2 RMII Receive AC Timing Specifications
The following table provides the RMII receive AC timing specifications.
Table 23. RMII Receive AC Timing Specifications
At recommended operating conditions with OV
DD
of 3.3 V ± 300mV.
Parameter/Condition Symbol
1
Min Typical Max Unit
REF_CLK clock period t
RMX
—20—ns
REF_CLK duty cycle t
RMXH
/t
RMX
35 — 65 %
RXD[1:0], CRS_DV, RX_ER setup time to REF_CLK t
RMRDVKH
4.0 — — ns
RXD[1:0], CRS_DV, RX_ER hold time to REF_CLK t
RMRDXKH
2.0 — — ns
REF_CLK clock rise V
IL
(min) to V
IH
(max) t
RMXR
1.0 — 4.0 ns
REF_CLK clock fall time V
IH
(max) to V
IL
(min) t
RMXF
1.0 — 4.0 ns
Note:
1. The symbols used for timing specifications follow the pattern of t
(first three letters of functional block)(signal)(state)(reference)(state)
for
inputs and t
(first two letters of functional block)(reference)(state)(signal)(state)
for outputs. For example, t
RMRDVKH
symbolizes RMII
receive timing (RMR) with respect to the time data input signals (D) reach the valid state (V) relative to the t
RMX
clock
reference (K) going to the high (H) state or setup time. Also, t
RMRDXKL
symbolizes RMII receive timing (RMR) with respect
to the time data input signals (D) went invalid (X) relative to the t
RMX
clock reference (K) going to the low (L) state or hold
time. Note that, in general, the clock reference symbol representation is based on three letters representing the clock of a
particular functional. For example, the subscript of t
RMX
represents the RMII (RM) reference (X) clock. For rise and fall times,
the latter convention is used with the appropriate letter: R (rise) or F (fall).
REF_CLK
TXD[1:0]
t
RMTKHDX
t
RMX
t
RMXH
t
RMXR
t
RMXF
TX_EN
