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MPC8306SCVMABDCA

P1-P3P4-P6P7-P9P10-P12P13-P15P16-P18P19-P21P22-P24P25-P27P28-P30P31-P33P34-P36P37-P39P40-P42P43-P45P46-P48P49-P51P52-P54P55-P57P58-P60P61-P63P64-P66P67-P69P70-P70
MPC8306S PowerQUICC II Pro Integrated Communications Processor Family Hardware Specifications, Rev. 1
Freescale Semiconductor 55
Clocking
20.1 System Clock Domains
As shown in Figure 38, the primary clock input (frequency) is multiplied up by the system phase-locked
loop (PLL) and the clock unit to create four major clock domains:
• The coherent system bus clock (csb_clk)
• The QUICC Engine clock (qe_clk)
• The internal clock for the DDR controller (ddr_clk)
• The internal clock for the local bus controller (lbc_clk)
The csb_clk frequency is derived from the following equation:
csb_clk = SYS_CLK_IN × SPMF Eqn. 1
The csb_clk serves as the clock input to the e300 core. A second PLL inside the core multiplies up the
csb_clk frequency to create the internal clock for the core (core_clk). The system and core PLL multipliers
are selected by the SPMF and COREPLL fields in the reset configuration word low (RCWL) which is
loaded at power-on reset or by one of the hard-coded reset options. For more information, see the Reset
Configuration chapter in the MPC8306S PowerQUICC II Pro Integrated Communications Processor
Family Reference Manual.
The qe_clk frequency is determined by the QUICC Engine PLL multiplication factor (RCWL[CEPMF])
and the QUICC Engine PLL division factor (RCWL[CEPDF]) as the following equation:
qe_clk = (QE_CLK_IN × CEPMF) (1 + CEPDF) Eqn. 2
qe_clk = (QE_CLK_IN × CEPMF)
(1 + CEPDF) Eqn. 3
For more information, see the QUICC Engine PLL Multiplication Factor section and the “QUICC Engine
PLL Division Factor” section in the MPC8306S PowerQUICC II Pro Integrated Communications
Processor Family Reference Manual for more information.
The DDR SDRAM memory controller operates with a frequency equal to twice the frequency of csb_clk.
Note that ddr_clk is not the external memory bus frequency; ddr_clk passes through the DDR clock divider
(2) to create the differential DDR memory bus clock outputs (MCK and MCK). However, the data rate
is the same frequency as ddr_clk.
The local bus memory controller operates with a frequency equal to the frequency of csb_clk. Note that
lbc_clk is not the external local bus frequency; lbc_clk passes through the LBC clock divider to create the
external local bus clock outputs (LCLK). The LBC clock divider ratio is controlled by LCRR[CLKDIV].
For more information, see the LBC Bus Clock and Clock Ratios section in the MPC8306S PowerQUICC
II Pro Integrated Communications Processor Family Reference Manual.
MPC8306S PowerQUICC II Pro Integrated Communications Processor Family Hardware Specifications, Rev. 1
56 Freescale Semiconductor
Clocking
In addition, some of the internal units may be required to be shut off or operate at lower frequency than
the csb_clk frequency. These units have a default clock ratio that can be configured by a memory mapped
register after the device comes out of reset.
The following table specifies which units have a configurable clock frequency. For detailed description,
refer to the “System Clock Control Register (SCCR)” section in the MPC8306S PowerQUICC II Pro
Integrated Communications Processor Family Reference Manual.
NOTE
Setting the clock ratio of these units must be performed prior to any access
to them.
The following table provides the maximum operating frequencies for the MPC8306S MAPBGA under
recommended operating conditions (see Table 2).
20.2 System PLL Configuration
The system PLL is controlled by the RCWL[SPMF] parameter. Table 49 shows the multiplication factor
encodings for the system PLL.
NOTE
System PLL VCO frequency = 2 × (CSB frequency) × (System PLL VCO
divider). The VCO divider needs to be set properly so that the System PLL
VCO frequency is in the range of 450–750 MHz.
As described in Section 20, “Clocking,” the LBCM, DDRCM, and SPMF parameters in the reset
configuration word low select the ratio between the primary clock input (SYS_CLK_IN) and the internal
Table 47. Configurable Clock Units
Unit Default Frequency Options
I2C,SDHC, USB, DMA Complex csb_clk Off, csb_clk, csb_clk/2, csb_clk/3
Table 48. Operating Frequencies for MAPBGA
Characteristic
1
Max Operating Frequency Unit
e300 core frequency (core_clk)266MHz
Coherent system bus frequency (csb_clk)133MHz
QUICC Engine frequency (qe_clk)233MHz
DDR2 memory bus frequency (MCLK)
2
167 MHz
Local bus frequency (LCLKn)
3
66 MHz
Notes:
1. The SYS_CLK_IN frequency, RCWL[SPMF], and RCWL[COREPLL] settings must be chosen such that the resulting
csb_clk, MCLK, LCLK, and core_clk frequencies do not exceed their respective maximum or minimum operating
frequencies.
2. The DDR2 data rate is 2× the DDR2 memory bus frequency.
3. The local bus frequency is 1/2, 1/4, or 1/8 of the lb_clk frequency (depending on LCRR[CLKDIV]) which is in turn 1× or 2×
the csb_clk frequency (depending on RCWL[LBCM]).
MPC8306S PowerQUICC II Pro Integrated Communications Processor Family Hardware Specifications, Rev. 1
Freescale Semiconductor 57
Clocking
coherent system bus clock (csb_clk). The following table shows the expected frequency values for the CSB
frequency for selected csb_clk to SYS_CLK_IN ratios.
20.3 Core PLL Configuration
RCWL[COREPLL] selects the ratio between the internal coherent system bus clock (csb_clk) and the e300
core clock (core_clk). The following table shows the encodings for RCWL[COREPLL]. COREPLL
values not listed, and should be considered reserved.
Table 49. System PLL Multiplication Factors
RCWL[SPMF] System PLL Multiplication Factor
0000 Reserved
0001 Reserved
0010 × 2
0011 × 3
0100 × 4
0101 × 5
0110 × 6
0111–1111 Reserved
Table 50. CSB Frequency Options
SPMF csb_clk : sys_clk_in Ratio
SYS_CLK_IN(MHz)
25 33.33 66.67
csb_clk Frequency (MHz)
0010 2:1
133
0011 3:1
0100 4:1 133
0101 5:1
125 167
0110 6:1
Table 51. e300 Core PLL Configuration
RCWL[COREPLL]
core_clk : csb_clk Ratio VCO Divider
0-1 2-5 6
nn 0000 n PLL bypassed
(PLL off, csb_clk clocks core directly)
PLL bypassed
(PLL off, csb_clk clocks core directly)
00 0001 0 1:1 2
01 0001 0 1:1 4
10 0001 0 1:1 8
11 0001 0 1:1 8
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MPC8306SCVMABDCA

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NXP / Freescale
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Microprocessors - MPU E300 MP ext tmp 133
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