MPC8306S PowerQUICC II Pro Integrated Communications Processor Family Hardware Specifications, Rev. 1
Freescale Semiconductor 13
DDR2 SDRAM
The following table provides the PLL lock times.
5.1 Reset Signals DC Electrical Characteristics
The following table provides the DC electrical characteristics for the MPC8306S reset signals mentioned
in Table 9.
6DDR2 SDRAM
This section describes the DC and AC electrical specifications for the DDR2 SDRAM interface of the
MPC8306S. Note that DDR2 SDRAM is GV
DD
(typ) = 1.8 V.
6.1 DDR2 SDRAM DC Electrical Characteristics
The following table provides the recommended operating conditions for the DDR2 SDRAM component(s)
of the MPC8306S when GV
DD
(typ) = 1.8 V.
Table 10. PLL Lock Times
Parameter/Condition Min Max Unit Note
PLL lock times 100 s—
Table 11. Reset Signals DC Electrical Characteristics
Characteristic Symbol Condition Min Max Unit Note
Output high voltage V
OH
I
OH
= –6.0 mA 2.4 V 1
Output low voltage V
OL
I
OL
= 6.0 mA 0.5 V 1
Output low voltage V
OL
I
OL
= 3.2 mA 0.4 V 1
Input high voltage V
IH
—2.0OV
DD
+0.3 V 1
Input low voltage V
IL
—–0.30.8V
Input current I
IN
0 V V
IN
OV
DD
— ±5 A—
Note:
1. This specification applies when operating from 3.3 V supply.
Table 12. DDR2 SDRAM DC Electrical Characteristics for GV
DD
(typ) = 1.8 V
Parameter/Condition Symbol Min Max Unit Note
I/O supply voltage GV
DD
1.7 1.9 V 1
I/O reference voltage MVREF 0.49 GV
DD
0.51 GV
DD
V2
I/O termination voltage V
TT
MVREF – 0.04 MVREF + 0.04 V 3
Input high voltage V
IH
MVREF+ 0.125 GV
DD
+0.3 V
Input low voltage V
IL
–0.3 MVREF – 0.125 V
Output leakage current I
OZ
–9.9 9.9 A4
MPC8306S PowerQUICC II Pro Integrated Communications Processor Family Hardware Specifications, Rev. 1
14 Freescale Semiconductor
DDR2 SDRAM
The following table provides the DDR2 capacitance when GV
DD
(typ) = 1.8 V.
6.2 DDR2 SDRAM AC Electrical Characteristics
This section provides the AC electrical characteristics for the DDR2 SDRAM interface.
6.2.1 DDR2 SDRAM Input AC Timing Specifications
This table provides the input AC timing specifications for the DDR2 SDRAM (GV
DD
(typ) = 1.8 V).
The following table provides the input AC timing specifications for the DDR2 SDRAM interface.
Output high current (V
OUT
= 1.35 V) I
OH
–13.4 mA
Output low current (V
OUT
= 0.280 V) I
OL
13.4 mA
Notes:
1. GV
DD
is expected to be within 50 mV of the DRAM GV
DD
at all times.
2. MVREF is expected to be equal to 0.5 GV
DD
, and to track GV
DD
DC variations as measured at the receiver. Peak-to-peak
noise on MVREF may not exceed ±2% of the DC value.
3. V
TT
is not applied directly to the device. It is the supply to which far end signal termination is made and is expected to be
equal to MVREF. This rail should track variations in the DC level of MVREF.
4. Output leakage is measured with all outputs disabled, 0 V
V
OUT
GV
DD
.
Table 13. DDR2 SDRAM Capacitance for GV
DD
(typ) = 1.8 V
Parameter/Condition Symbol Min Max Unit Note
Input/output capacitance: DQ, DQS C
IO
68pF1
Delta input/output capacitance: DQ, DQS C
DIO
—0.5pF1
Note:
1. This parameter is sampled. GV
DD
= 1.8 V ± 0.100 V, f = 1 MHz, T
A
=2C, V
OUT
= GV
DD
2,
V
OUT
(peak-to-peak) = 0.2 V.
Table 14. DDR2 SDRAM Input AC Timing Specifications for 1.8-V Interface
At recommended operating conditions with GV
DD
of 1.8 V± 100mV.
Parameter Symbol Min Max Unit Note
AC input low voltage V
IL
MVREF
– 0.25 V
AC input high voltage V
IH
MVREF
+ 0.25 V
Table 15. DDR2 SDRAM Input AC Timing Specifications
At recommended operating conditions with GV
DD
of 1.8V ± 100mV.
Parameter Symbol Min Max Unit Note
Controller skew for MDQS—MDQ/MDM t
CISKEW
ps 1, 2
Table 12. DDR2 SDRAM DC Electrical Characteristics for GV
DD
(typ) = 1.8 V (continued)
Parameter/Condition Symbol Min Max Unit Note
MPC8306S PowerQUICC II Pro Integrated Communications Processor Family Hardware Specifications, Rev. 1
Freescale Semiconductor 15
DDR2 SDRAM
The following figure shows the input timing diagram for the DDR controller.
Figure 4. DDR Input Timing Diagram
6.2.2 DDR2 SDRAM Output AC Timing Specifications
The following table provides the output AC timing specifications for the DDR2 SDRAM interfaces.
266 MHz –750 750
Notes:
1. t
CISKEW
represents the total amount of skew consumed by the controller between MDQS[n] and any corresponding bit that
is captured with MDQS[n]. This should be subtracted from the total timing budget.
2. The amount of skew that can be tolerated from MDQS to a corresponding MDQ signal is called t
DISKEW
. This can be
determined by the equation: t
DISKEW
= ±(T/4 – abs(t
CISKEW
)) where T is the clock period and abs(t
CISKEW
) is the absolute
value of t
CISKEW
.
Table 16. DDR2 SDRAM Output AC Timing Specifications
At recommended operating conditions with GV
DD
of 1.8V ± 100mV.
Parameter Symbol
1
Min Max Unit Note
MCK cycle time, (MCK/MCK
crossing) t
MCK
5.988 8 ns 2
ADDR/CMD output setup with respect to MCK t
DDKHAS
ns 3
266 MHz 2.5
ADDR/CMD output hold with respect to MCK t
DDKHAX
ns 3
266 MHz 2.5
MCS
output setup with respect to MCK t
DDKHCS
ns 3
266 MHz 2.5
Table 15. DDR2 SDRAM Input AC Timing Specifications (continued)
At recommended operating conditions with GV
DD
of 1.8V ± 100mV.
Parameter Symbol Min Max Unit Note
MCK[n]
MCK[n]
t
MCK
MDQ[x]
MDQS[n]
t
DISKEW
D1D0
t
DISKEW

MPC8306SCVMABDCA

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Microprocessors - MPU E300 MP ext tmp 133
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