MPC8306S PowerQUICC II Pro Integrated Communications Processor Family Hardware Specifications, Rev. 1
Freescale Semiconductor 7
Electrical Characteristics
Input voltage DDR2 DRAM signals MV
IN
–0.3 to (GV
DD
+0.3) V 3
DDR2 DRAM reference MV
REF
–0.3 to (GV
DD
+0.3) V 3
Local bus, DUART, SYS_CLK_IN,
system control and power
management, I
2
C, SPI, and JTAG
signals
OV
IN
–0.3 to (OV
DD
+0.3) V 4
Storage temperature range T
STG
55to150 C—
Notes:
1. Functional and tested operating conditions are given in Table 2. Absolute maximum ratings are stress ratings only, and
functional operation at the maximums is not guaranteed. Stresses beyond those listed may affect device reliability or cause
permanent damage to the device.
2. OVDD here refers to NVDDA, NVDDB, NVDDC, NVDDF, NVDDG, and NVDDH from the ball map.
3. Caution: MV
IN
must not exceed GV
DD
by more than 0.3 V. This limit may be exceeded for a maximum of 100 ms during
power-on reset and power-down sequences.
4. Caution: OV
IN
must not exceed OV
DD
by more than 0.3 V. This limit may be exceeded for a maximum of 100 ms during
power-on reset and power-down sequences.
Table 1. Absolute Maximum Ratings
1
(continued)
Characteristic Symbol Max Value Unit Notes
MPC8306S PowerQUICC II Pro Integrated Communications Processor Family Hardware Specifications, Rev. 1
8 Freescale Semiconductor
Electrical Characteristics
2.1.2 Power Supply Voltage Specification
The following table provides the recommended operating conditions for the MPC8306S. Note that these
values are the recommended and tested operating conditions. Proper device operation outside of these
conditions is not guaranteed.
The following figure shows the undershoot and overshoot voltages at the interfaces of the MPC8306S
Figure 2. Overshoot/Undershoot Voltage for GV
DD
/OV
DD
Table 2. Recommended Operating Conditions
Characteristic Symbol
Recommended
Value
Unit Note
Core supply voltage V
DD
1.0 V ± 50 mV V 1
PLL supply voltage AV
DD1
AV
DD2
AV
DD3
1.0 V ± 50 mV V 1
DDR2 DRAM I/O voltage GV
DD
1.8 V ± 100 mV V 1
Local bus, DUART, system control and power management, I
2
C,
SPI, MII, RMII, MII management, USB and JTAG I/O voltage
OV
DD
3.3 V ± 300 mV V 1, 3
Junction temperature T
A
/T
J
0to105 C2
Notes:
1. GV
DD
, OV
DD
, AV
DD
, and V
DD
must track each other and must vary in the same direction—either in the positive or negative
direction.
2. Minimum temperature is specified with T
A
(Ambient Temperature); maximum temperature is specified with T
J
(Junction
Temperature).
3. OVDD here refers to NVDDA, NVDDB, NVDDC, NVDDF, NVDDG, and NVDDH from the ball map.
GND
GND – 0.3 V
GND – 0.7 V
Not to Exceed 10%
G/OV
DD
+ 20%
G/OV
DD
G/OV
DD
+ 5%
of t
interface
1
1. t
interface
refers to the clock period associated with the bus clock interface.
V
IH
V
IL
Note:
MPC8306S PowerQUICC II Pro Integrated Communications Processor Family Hardware Specifications, Rev. 1
Freescale Semiconductor 9
Electrical Characteristics
2.1.3 Output Driver Characteristics
The following table provides information on the characteristics of the output driver strengths.
2.1.4 Input Capacitance Specification
The following table describes the input capacitance for the SYS_CLK_IN pin in the MPC8306S.
2.2 Power Sequencing
The device does not require the core supply voltage (V
DD
) and I/O supply voltages (GV
DD
and OV
DD
) to
be applied in any particular order. Note that during power ramp-up, before the power supplies are stable
and if the I/O voltages are supplied before the core voltage, there might be a period of time that all input
and output pins are actively driven and cause contention and excessive current. In order to avoid actively
driving the I/O pins and to eliminate excessive current draw, apply the core voltage (V
DD
) before the I/O
voltage (GV
DD
and OV
DD
) and assert PORESET before the power supplies fully ramp up. In the case
where the core voltage is applied first, the core voltage supply must rise to 90% of its nominal value before
the I/O supplies reach 0.7 V; see Figure 3. Once both the power supplies (I/O voltage and core voltage) are
stable, wait for a minimum of 32 clock cycles before negating PORESET.
NOTE
There is no specific power down sequence requirement for the device. I/O
voltage supplies (GV
DD
and OV
DD
) do not have any ordering requirements
with respect to one another.
Table 3. Output Drive Capability
Driver Type
Output Impedance
()
Supply Voltage (V)
Local bus interface utilities signals 42 OV
DD
=3.3
DDR2 signal 18 GV
DD
=1.8
DUART, system control, I2C, SPI, JTAG 42 OV
DD
=3.3
GPIO signals 42 OV
DD
=3.3
Table 4. Input Capacitance Specification
Parameter/Condition Symbol Min Max Unit Note
Input capacitance for all pins except SYS_CLK_IN and
QE_CLK_IN
C
I
68pF
Input capacitance for SYS_CLK_IN and QE_CLK_IN C
ICLK_IN
10 pF 1
Note:
1. The external clock generator should be able to drive 10 pF.

MPC8306SCVMABDCA

Mfr. #:
Manufacturer:
NXP / Freescale
Description:
Microprocessors - MPU E300 MP ext tmp 133
Lifecycle:
New from this manufacturer.
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