UJA1075_2 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2010. All rights reserved.
Product data sheet Rev. 02 — 27 May 2010 10 of 53
NXP Semiconductors
UJA1075
High-speed CAN/LIN core system basis chip
• The chip temperature rises above the OTP activation threshold, T
th(act)otp
, causing the
SBC to switch to Overtemp mode
6.1.5 Sleep mode
Sleep mode is selected from Standby mode or Normal mode by setting bits MC in the
Mode_Control register (Table 5
) to 01. The SBC will enter Sleep mode providing there are
no pending interrupts (INTN = HIGH) or wake-up events and at least one wake-up source
is enabled (CAN, LIN or WAKE). Any attempt to enter Sleep mode while one of these
conditions has not been satisfied will result in a short reset (3.6 ms min. pulse width; see
Section 6.5.1
and Table 11).
In Sleep mode, V1 and V2 are off and the bus transceivers will be switched off (Off mode;
STBCC/STBCL = 0; see Table 6
) or in a low-power state (Lowpower mode;
STBCC/STBCL = 1) with bus wake-up detection active - see Section 6.7.1
and
Section 6.8.1
). The watchdog is off and the reset pin is LOW.
A CAN, LIN or local wake-up event will cause the SBC to switch from Sleep mode to
Standby mode, generating a (short or long; see Section 6.5.1
) system reset. The value of
the mode control bits (MC) will be changed to 00 and V1 will be enabled.
6.1.6 Overtemp mode
The SBC will enter Overtemp mode from Normal mode or Standby mode when the chip
temperature exceeds the overtemperature protection activation threshold, T
th(act)otp
,
In Overtemp mode, the voltage regulators are switched off and the bus systems are in a
high-resistive state. When the SBC enters Overtemp mode, the RSTN pin is driven LOW
and the limp home control bit, LHC, is set so that the LIMP pin is driven LOW.
The chip temperature must drop a hysteresis level below the overtemperature shutdown
threshold before the SBC can exit Overtemp mode. After leaving Overtemp mode the
SBC enters Standby mode and a system reset is generated (reset pulse width of t
w(rst)
,
long or short; see Section 6.5.1
and Table 11).
6.2 SPI
6.2.1 Introduction
The Serial Peripheral Interface (SPI) provides the communication link with the
microcontroller, supporting multi-slave operations. The SPI is configured for full duplex
data transfer, so status information is returned when new control data is shifted in. The
interface also offers a read-only access option, allowing registers to be read back by the
application without changing the register content.
The SPI uses four interface signals for synchronization and data transfer:
• SCSN: SPI chip select; active LOW
• SCK: SPI clock; default level is LOW due to low-power concept
• SDI: SPI data input
• SDO: SPI data output; floating when pin SCSN is HIGH
Bit sampling is performed on the falling clock edge and data is shifted on the rising clock
edge (see Figure 4
).
