OMO ElectronicOMO Electronic
Expand menu
Hello, Sign inMy Account
0 Cart

UJA1075TW/3V3,112

P1-P3P4-P6P7-P9P10-P12P13-P15P16-P18P19-P21P22-P24P25-P27P28-P30P31-P33P34-P36P37-P39P40-P42P43-P45P46-P48P49-P51P52-P53
UJA1075_2 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2010. All rights reserved.
Product data sheet Rev. 02 — 27 May 2010 43 of 53
NXP Semiconductors
UJA1075
High-speed CAN/LIN core system basis chip
[7] The watchdog will be reset if it is in window mode and is triggered at least t
trig(wd)1
, but not more than t
trig(wd)2
, after the start of the
watchdog period (or in the second half of the watchdog period). A system reset will be performed if the watchdog is triggered more than
t
trig(wd)2
after the start of the watchdog period (watchdog overflows).
Fig 15. Timing test circuit for CAN transceiver
Fig 16. CAN transceiver timing diagram
SBC
BAT
CANL
CANH
TXDC
R
CANH
−
R
CANL
RXDC
C
RXDC
GND
C
CANH
− C
CANL
015aaa079
CANH
CANL
t
d(TXDC-busdom)
TXDC
V
O(dif)bus
RXDC
HIGH
HIGH
LOW
LOW
dominant
recessive
0.9 V
0.5 V
t
d(busdom-RXDC)
t
d(TXDC-busrec)
t
d(busrec-RXDC)
t
d(TXDCH-RXDCH)
t
d(TXDCL-RXDCL)
015aaa15
1
UJA1075_2 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2010. All rights reserved.
Product data sheet Rev. 02 — 27 May 2010 44 of 53
NXP Semiconductors
UJA1075
High-speed CAN/LIN core system basis chip
Fig 17. Timing test circuit for LIN transceiver
SBC
BAT
DLIN
TXDL
R
LIN
C
LIN
RXDL
C
RXDL
LIN
GND
015aaa12
8
Fig 18. LIN transceiver timing diagram
015aaa133
V
TXDL
LIN bus signal
V
BAT
t
bit
t
bus(rec)(min)
V
th(rec)RX(max)
thresholds of
receiving node A
V
th(dom)RX(max)
V
th(rec)RX(min)
V
th(dom)RX(min)
t
PD(RX)r
t
PD(RX)f
t
PD(RX)r
t
PD(RX)f
t
bus(rec)(max)
t
bit
t
bit
thresholds of
receiving node B
output of receiving
node A
V
RXDL
output of receiving
node B
V
RXDL
t
bus(dom)(max)
t
bus(dom)(min)
UJA1075_2 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2010. All rights reserved.
Product data sheet Rev. 02 — 27 May 2010 45 of 53
NXP Semiconductors
UJA1075
High-speed CAN/LIN core system basis chip
11. Test information
11.1 Quality information
This product has been qualified in accordance with the Automotive Electronics Council
(AEC) standard Q100 - Failure mechanism based stress test qualification for integrated
circuits, and is suitable for use in automotive applications.
Fig 19. SPI timing diagram
015aaa04
5
SCS
SCK
SDI
SDO X
X X
MSB LSB
MSB LSB
t
v(Q)
floating floating
t
h(D)
t
su(D)
t
clk(L)
t
clk(H)
t
SPILEAD
T
cy(clk)
t
SPILAG
t
WH(S)
P1-P3P4-P6P7-P9P10-P12P13-P15P16-P18P19-P21P22-P24P25-P27P28-P30P31-P33P34-P36P37-P39P40-P42P43-P45P46-P48P49-P51P52-P53

UJA1075TW/3V3,112

Mfr. #:
Buy UJA1075TW/3V3,112
Manufacturer:
NXP Semiconductors
Description:
IC SBC CAN/LIN HS 3.3V 32HTSSOP
Lifecycle:
New from this manufacturer.
Delivery:
DHL FedEx Ups TNT EMS
Payment:
T/T Paypal Visa MoneyGram Western Union

Products related to this Datasheet