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UJA1075TW/3V3,112

P1-P3P4-P6P7-P9P10-P12P13-P15P16-P18P19-P21P22-P24P25-P27P28-P30P31-P33P34-P36P37-P39P40-P42P43-P45P46-P48P49-P51P52-P53
UJA1075_2 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2010. All rights reserved.
Product data sheet Rev. 02 — 27 May 2010 13 of 53
NXP Semiconductors
UJA1075
High-speed CAN/LIN core system basis chip
6.2.4 Mode_Control register
[1] Bit LHWC is set to 1 after a reset.
[2] Bit LHC is set to 1 after a reset, if LHWC was set to 1 prior to the reset.
Table 5. Mode_Control register
Bit Symbol Access Power-on
default
Description
15:13 A2, A1, A0 R 001 register address
12 RO R/W 0 access status
0: register set to read/write
1: register set to read only
11:10 MC R/W 00 mode control
00: Standby mode
01: Sleep mode
10: Normal mode; V2 off
11: Normal mode; V2 on
9LHWC
[1]
R/W 1 limp home warning control
0: no limp home warning
1: limp home warning is set; next reset will activate LIMP output
8LHC
[2]
R/W 0 limp home control
0: LIMP pin set floating
1: LIMP pin driven LOW
7 ENC R/W 0 enable control
0: EN pin driven LOW
1: EN pin driven HIGH in Normal mode
6 LSC R/W 0 LIN slope control
0: normal slope, 20 kbit/s
1: low slope, 10.4 kbit/s
5 WBC R/W 0 wake bias control
0: WBIAS floating if WSEn = 0; 16 ms sampling if WSEn = 1
1: WBIAS on if WSEn = 0; 64 ms sampling if WSEn = 1
4 PDC R/W 0 power distribution control
0: V1 threshold current for activating the external PNP transistor; load current
rising; I
th(act)PNP
= 85 mA; V1 threshold current for deactivating the external
PNP transistor; load current falling; I
th(deact)PNP
=50mA; see Figure 7
1: V1 threshold current for activating the external PNP transistor; load current
rising; I
th(act)PNP
= 50 mA; V1 threshold current for deactivating the external
PNP transistor; load current falling; I
th(deact)PNP
=15mA; see Figure 7
3:0 reserved R 0000
UJA1075_2 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2010. All rights reserved.
Product data sheet Rev. 02 — 27 May 2010 14 of 53
NXP Semiconductors
UJA1075
High-speed CAN/LIN core system basis chip
6.2.5 Int_Control register
Table 6. Int_Control register
Bit Symbol Access Power-on
default
Description
15:13 A2, A1, A0 R 010 register address
12 RO R/W 0 access status
0: register set to read/write
1: register set to read only
11 V1UIE R/W 0 V1 undervoltage interrupt enable
0: V1 undervoltage warning interrupts cannot be requested
1: V1 undervoltage warning interrupts can be requested
10 V2UIE R/W 0 V2 undervoltage interrupt enable
0: V2 undervoltage warning interrupts cannot be requested
1: V2 undervoltage warning interrupts can be requested
9 STBCL R/W 0 LIN standby control
0: When the SBC is in Normal mode (MC = 1x):
LIN is in Active mode. The wake-up flag (visible on RXDL) is cleared
regardless of the value of V
BAT
.
When the SBC is in Standby/Sleep mode (MC = 0x):
LIN is in Off mode. Bus wake-up detection is disabled. LIN wake-up
interrupts cannot be requested.
1: LIN is in Lowpower mode with bus wake-up detection enabled, regardless
of the SBC mode (MC = xx). LIN wake-up interrupts can be requested.
8 reserved R 0
7:6 WIC1 R/W 00 wake-up interrupt 1 control
00: wake-up interrupt 1 disabled
01: wake-up interrupt 1 on rising edge
10: wake-up interrupt 1 on falling edge
11: wake-up interrupt 1 on both edges
5:4 WIC2 R/W 00 wake-up interrupt 2 control
00: wake-up interrupt 2 disabled
01: wake-up interrupt 2 on rising edge
10: wake-up interrupt 2 on falling edge
11: wake-up interrupt 2 on both edges
3 STBCC R/W 0 CAN standby control
0: When the SBC is in Normal mode (MC = 1x):
CAN is in Active mode. The wake-up flag (visible on RXDC) is cleared
regardless of V2 output voltage.
When the SBC is in Standby/Sleep mode (MC = 0x):
CAN is in Off mode. Bus wake-up detection is disabled. CAN wake-up
interrupts cannot be requested.
1: CAN is in Lowpower mode with bus wake-up detection enabled,
regardless of the SBC mode (MC = xx). CAN wake-up interrupts can be
requested.
UJA1075_2 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2010. All rights reserved.
Product data sheet Rev. 02 — 27 May 2010 15 of 53
NXP Semiconductors
UJA1075
High-speed CAN/LIN core system basis chip
2 RTHC R/W 0 reset threshold control
0: The reset threshold is set to the 90 % V1 undervoltage detection voltage
(V
uvd
; see Table 10)
1: The reset threshold is set to the 70 % V1 undervoltage detection voltage
(V
uvd
; see Table 10)
1 WSE1 R/W 0 WAKE1 sample enable
0: sampling continuously
1: sampling of WAKE1 is synchronized with WBIAS (sample rate controlled
by WBC)
0 WSE2 R/W 0 WAKE2 sample enable
0: sampling continuously
1: sampling of WAKE1 is synchronized with WBIAS (sample rate controlled
by WBC)
Table 6. Int_Control register
Bit Symbol Access Power-on
default
Description
P1-P3P4-P6P7-P9P10-P12P13-P15P16-P18P19-P21P22-P24P25-P27P28-P30P31-P33P34-P36P37-P39P40-P42P43-P45P46-P48P49-P51P52-P53

UJA1075TW/3V3,112

Mfr. #:
Buy UJA1075TW/3V3,112
Manufacturer:
NXP Semiconductors
Description:
IC SBC CAN/LIN HS 3.3V 32HTSSOP
Lifecycle:
New from this manufacturer.
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