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UJA1075TW/3V3,112

P1-P3P4-P6P7-P9P10-P12P13-P15P16-P18P19-P21P22-P24P25-P27P28-P30P31-P33P34-P36P37-P39P40-P42P43-P45P46-P48P49-P51P52-P53
UJA1075_2 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2010. All rights reserved.
Product data sheet Rev. 02 — 27 May 2010 19 of 53
NXP Semiconductors
UJA1075
High-speed CAN/LIN core system basis chip
The reset pulse width (t
w(rst)
) is selectable (short or long) if the system reset was
generated by a V1 undervoltage event (see Section 6.6.2
) or by the SBC leaving Off
(V
BAT
> V
th(det)pon
) or Overtemp (temperature < T
th(rel)otp
) modes. A short reset pulse is
selected by connecting a 900 Ω ±10 % resistor between pins RSTN and V1. If a resistor is
not connected, the reset pulse will be long (see Table 11
).
In all other cases (e.g. watchdog-related reset events) the reset pulse length will be short.
6.5.2 EN output
The EN pin can be used to control external hardware, such as power components, or as a
general-purpose output when the system is running properly.
In Normal and Standby modes, the microcontroller can set the EN control bit (bit ENC in
the Mode_Control register; see Table 5
) via the SPI interface. Pin EN will be HIGH when
ENC = 1 and MC = 10 or 11. A reset event will cause pin EN to go LOW. EN pin behavior
is illustrated in Figure 5
.
6.5.3 LIMP output
The LIMP pin can be used to enable the so called ‘limp home’ hardware in the event of an
ECU failure. Detectable failure conditions include SBC overtemperature events, loss of
watchdog service, RSTN or V1 clamped LOW and user-initiated or external reset events.
The LIMP pin is a battery-related, active-LOW, open-drain output.
A system reset will cause the limp home warning control bit (bit LHWC in the
Mode_Control register; see Table 5
) to be set. If LHWC is already set when the system
reset is generated, bit LHC will be set which will force the LIMP pin LOW. The application
should clear LHWC after each reset event to ensure the LIMP output is not activated
during normal operation.
In Overtemp mode, bit LHC is always set and, consequently, the LIMP output is always
active. If the application manages to recover from the event that activated the LIMP
output, LHC can be cleared to deactivate the LIMP output.
Fig 5. Behavior of EN pin
RSTN
EN
ENC
mode
STANDBY NORMAL STANDBY
015aaa07
4
UJA1075_2 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2010. All rights reserved.
Product data sheet Rev. 02 — 27 May 2010 20 of 53
NXP Semiconductors
UJA1075
High-speed CAN/LIN core system basis chip
6.6 Power supplies
6.6.1 Battery pin (BAT)
The SBC contains a single supply pin, BAT. An external diode is needed in series to
protect the device against negative voltages. The operating range is from 4.5 V to 28 V.
The SBC can handle maximum voltages up to 40 V.
If the voltage on pin BAT falls below the power-off detection threshold, V
th(det)poff
, the SBC
immediately enters Off mode, which means that the voltage regulators and the internal
logic are shut down. The SBC leaves Off mode for Standby mode as soon as the voltage
rises above the power-on detection threshold, V
th(det)pon
. The POSI bit in the Int_Status
register is set to 1 when the SBC leaves Off mode.
6.6.2 Voltage regulator V1
Voltage regulator V1 is intended to supply the microcontroller, its periphery and additional
transceivers. V1 is supplied by pin BAT and delivers up to 250 mA at 3.3 V or 5 V
(depending on the UJA1075 version).
To prevent the device overheating at high ambient temperatures or high average currents,
an external PNP transistor can be connected as illustrated in Figure 6
. In this
configuration, the power dissipation is distributed between the SBC and the PNP
transistor. Bit PDC in the Mode_Control register (Table 5
) is used to regulate how the
power dissipation is distributed − if PDC = 0, the PNP transistor will be activated when the
load current reaches 85 mA (50 mA if PDC = 1) at T
vj
=150°C. V1 will continue to deliver
85 mA while the transistor delivers the additional load current (see Figure 7
and Figure 8).
Fig 6. External PNP transistor control circuit
UJA107x
VEXCTRL
V1
VEXCC
015aaa098
BAT
battery
UJA1075_2 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2010. All rights reserved.
Product data sheet Rev. 02 — 27 May 2010 21 of 53
NXP Semiconductors
UJA1075
High-speed CAN/LIN core system basis chip
Figure 7 illustrates how V1 and the PNP transistor combine to supply a slow ramping load
current of 250 mA with PDC = 0. Any additional load current requirement will be supplied
by the PNP transistor, up to its current limit. If the load current continues to rise, I
V1
will
increase above the selected PDC threshold (to a maximum of 250 mA).
For a fast ramping load current, V1 will deliver the required load current (to a maximum of
250 mA) until the PNP transistor has switched on. Once the transistor has been activated,
V1 will deliver 85 mA (PDC = 0) with the transistor contributing the balance of the load
current (see Figure 8
).
Fig 7. V1 and PNP currents at a slow ramping load current of 250 mA (PDC = 0)
Fig 8. V1 and PNP currents at a fast ramping load current of 250 mA (PDC = 0)
015aaa11
1
250 mA
85 mA
50 mA
load
current
215 mA
165 mA
PNP
current
I
V1
I
th(act)PNP
= 85 mA
(PDC = 0)
I
th(deact)PNP
= 50 mA
(PDC = 0)
load
current
250 mA
−165 mA
0 mA
I
V1
165 mA
250 mA
PNP
current
015aaa075
I
th(act)PNP
= 85 mA
(PDC = 0)
P1-P3P4-P6P7-P9P10-P12P13-P15P16-P18P19-P21P22-P24P25-P27P28-P30P31-P33P34-P36P37-P39P40-P42P43-P45P46-P48P49-P51P52-P53

UJA1075TW/3V3,112

Mfr. #:
Buy UJA1075TW/3V3,112
Manufacturer:
NXP Semiconductors
Description:
IC SBC CAN/LIN HS 3.3V 32HTSSOP
Lifecycle:
New from this manufacturer.
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