UJA1075_2 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2010. All rights reserved.
Product data sheet Rev. 02 — 27 May 2010 25 of 53
NXP Semiconductors
UJA1075
High-speed CAN/LIN core system basis chip
6.8.1 LIN operating modes
6.8.1.1 Active mode
The LIN transceiver will be in Active mode when:
• the SBC is in Normal mode (MC = 10 or 11) and
• the transceiver is enabled (STBCL = 0; see Table 6) and
• the battery voltage (V
BAT
) is above the LIN undervoltage recovery threshold, V
uvr(LIN)
.
In LIN Active mode, the transceiver can transmit and receive data via the LIN bus pin.
The receiver detects data streams on the LIN bus pin (LIN) and transfers them to the
microcontroller via pin RXDL (see Figure 1
) - LIN recessive is represented by a HIGH
level on RXDL, LIN dominant by a LOW level.
The transmit data streams of the protocol controller at the TXDL input (pin TXDL) are
converted by the transmitter into bus signals with optimized slew rate and wave shaping to
minimize EME.
6.8.1.2 Lowpower/Off modes
The LIN transceiver will be in Lowpower mode with bus wake-up detection enabled if bit
STBCL = 1 (see Table 6
). The LIN transceiver can be woken up remotely via pin LIN in
Lowpower mode.
When the SBC is in Standby mode or Sleep mode (MC = 00 or 01), the LIN transceiver
will be in Off mode if bit STBCL = 0. The LIN transceiver is powered down completely in
Off mode to minimize quiescent current consumption.
Filters at the receiver inputs prevent unwanted wake-up events due to automotive
transients or EMI.
The wake-up event must remain valid for at least the minimum dominant bus time for
wake-up of the LIN transceiver, t
wake(busdom)min
(see Table 11).
6.8.2 Fail-safe features
6.8.2.1 General fail-safe features
The following fail-safe features have been implemented:
• Pin TXDL has an internal pull-up towards V
V1
to guarantee a safe, defined state if this
pin is left floating
• The current of the transmitter output stage is limited in order to protect the transmitter
against short circuits to pin BAT
• A loss of power (pins BAT and GND) has no impact on the bus lines or on the
microcontroller. There will be no reverse currents from the bus.
6.8.2.2 TXDL dominant time-out function
A TXDL dominant time-out timer circuit prevents the bus lines being driven to a permanent
dominant state (blocking all network communications) if TXDL is forced permanently LOW
by a hardware and/or software application failure. The timer is triggered by a negative
