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UJA1075TW/3V3,112

P1-P3P4-P6P7-P9P10-P12P13-P15P16-P18P19-P21P22-P24P25-P27P28-P30P31-P33P34-P36P37-P39P40-P42P43-P45P46-P48P49-P51P52-P53
UJA1075_2 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2010. All rights reserved.
Product data sheet Rev. 02 — 27 May 2010 22 of 53
NXP Semiconductors
UJA1075
High-speed CAN/LIN core system basis chip
For short-circuit protection, a resistor needs to be connected between pins V1 and
VEXCC to allow the current to be monitored. This resistor limits the current delivered by
the external transistor. If the voltage difference between pins VEXCC and V1 reaches
V
th(act)Ilim
, the PNP current limiting activation threshold voltage, the transistor current will
not increase further.
The thermal performance of the transistor needs to be considered when calculating the
value of this resistor. A 3.3 Ω resistor was used with the BCP52-16 (NXP Semiconductors)
employed during testing. Note that the selection of the transistor is not critical. In general,
any PNP transistor with a current amplification factor (β) of between 60 and 500 can be
used.
If an external PNP transistor is not used, pin VEXCC must be connected to V1 while pin
VEXCTRL can be left open.
One advantage of this scalable voltage regulator concept is that there are no PCB layout
restrictions when using the external PNP. The distance between the UJA1075 and the
external PNP doesn’t affect the stability of the regulator loop because the loop is realized
within the UJA1075. Therefore, it is recommended that the distance between the
UJA1075 and PNP transistor be maximized for optimal thermal distribution.
The output voltage on V1 is monitored continuously and a system reset signal is
generated if an undervoltage event occurs. A system reset is generated if the voltage on
V1 falls below the undervoltage detection voltage (V
uvd
; see Table 10). The reset
threshold (90 % or 70 % of the nominal value) is set via the Reset Threshold Control bit
(RTHC) in the Int_Control register (Table 6
). In addition, an undervoltage warning (a V1UI
interrupt) will be generated at 90 % of the nominal output voltage. The status of V1 can be
read via bit V1S in the WD_and_Status register (Table 4
).
6.6.3 Voltage regulator V2
Voltage regulator V2 is reserved for the high-speed CAN transceiver, providing a 5 V
supply.
V2 can be activated and deactivated via the MC bits in the Mode_Control register
(Table 5
). An undervoltage warning (a V2UI interrupt) is generated when the output
voltage drops below 90 % of its nominal value. The status of V2 can be read via bit V2S in
the WD_and_Status register (Table 4
) in Normal mode (V2S = 1 in all other modes).
V2 can be deactivated (MC = 10) to allow the internal CAN transceiver to be supplied from
an external source or from V1. The alternative voltage source must be connected to pin
V2. All internal functions (e.g. undervoltage protection) will work normally.
6.7 CAN transceiver
The analog section of the UJA1075 CAN transceiver corresponds to that integrated into
the TJA1042/TJA1043. The transceiver is designed for high-speed (up to 1 Mbit/s) CAN
applications in the automotive industry, providing differential transmit and receive
capability to a CAN protocol controller.
6.7.1 CAN operating modes
6.7.1.1 Active mode
The CAN transceiver is in Active mode when:
UJA1075_2 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2010. All rights reserved.
Product data sheet Rev. 02 — 27 May 2010 23 of 53
NXP Semiconductors
UJA1075
High-speed CAN/LIN core system basis chip
• the SBC is in Normal mode (MC = 10 or 11)
• the transceiver is enabled (bit STBCC = 0; see Table 6)
and
• V2 is enabled and its output voltage is above its undervoltage threshold, V
uvd
or
• V2 is disabled but an external voltage source, or V1, connected to pin V2 is above its
undervoltage threshold (see Section 6.6.3
)
In CAN Active mode, the transceiver can transmit and receive data via the CANH and
CANL pins. The differential receiver converts the analog data on the bus lines into digital
data which is output on pin RXDC. The transmitter converts digital data generated by a
CAN controller, and input on pin TXDC, to signals suitable for transmission over the bus
lines.
6.7.1.2 Lowpower/Off modes
The CAN transceiver will be in Lowpower mode with bus wake-up detection enabled if bit
STBCC = 1 (see Table 6
). The CAN transceiver can be woken up remotely via pins CANH
and CANL in Lowpower mode.
When the SBC is in Standby mode or Sleep mode (MC = 00 or 01), the CAN transceiver
will be in Off mode if bit STBCC = 0. The CAN transceiver is powered down completely in
Off mode to minimize quiescent current consumption.
A filter at the receiver input prevents unwanted wake-up events occurring due to
automotive transients or EMI.
A recessive-dominant-recessive-dominant sequence must occur on the CAN bus within
the wake-up timeout time (t
to(wake)
) to pass the wake-up filter and trigger a wake-up event
(see Figure 9
; note that additional pulses may occur between the recessive/dominant
phases). The minimum recessive/dominant bus times for CAN transceiver wake-up
(t
wake(busrec)min
and t
wake(busdom)min
) must be satisfied (see Table 11).
Fig 9. CAN wake-up timing diagram
recessivedominantrecessive dominant
wake-up
015aaa10
7
t
wake
< t
to(wake)
UJA1075_2 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2010. All rights reserved.
Product data sheet Rev. 02 — 27 May 2010 24 of 53
NXP Semiconductors
UJA1075
High-speed CAN/LIN core system basis chip
6.7.2 Split circuit
Pin SPLIT provides a DC stabilized voltage of 0.5V
V2
. It is activated in CAN Active mode
only. Pin SPLIT is floating in CAN Lowpower and Off modes. The V
SPLIT
circuit can be
used to stabilize the recessive common-mode voltage by connecting pin SPLIT to the
center tap of the split termination (see Figure 10
).
A transceiver in the network that is not supplied and that generates a significant leakage
current from the bus lines to ground, can result in a recessive bus voltage of < 0.5V
V2
. In
this event, the split circuit will stabilize the recessive voltage at 0.5V
V2
. So a start of
transmission will not generate a step in the common-mode signal which would lead to
poor ElectroMagnetic Emission (EME) performance.
6.7.3 Fail-safe features
6.7.3.1 TXDC dominant time-out function
A TXDC dominant time-out timer is started when pin TXDC is forced LOW. If the LOW
state on pin TXDC persists for longer than the TXDC dominant time-out time (t
to(dom)TXDC
),
the transmitter will be disabled, releasing the bus lines to recessive state. This function
prevents a hardware and/or software application failure from driving the bus lines to a
permanent dominant state (blocking all network communications). The TXDC dominant
time-out timer is reset when pin TXDC goes HIGH. The TXDC dominant time-out time
also defines the minimum possible bit rate of 10 kbit/s.
6.7.3.2 Pull-up on TXDC pin
Pin TXDC has an internal pull-up towards V
V1
to ensure a safe defined state in case the
pin is left floating.
6.8 LIN transceiver
The analog sections of the UJA1075 LIN transceiver is identical to that integrated into the
TJA1021.
The transceiver is the interface between the LIN master/slave protocol controller and the
physical bus in a LIN. It is primarily intended for in-vehicle sub-networks using baud rates
from 1 kBd up to 20 kBd and is LIN 2.0/LIN 2.1/SAE J2602 compliant.
Fig 10. Stabilization circuitry and application using the SPLIT pin
UJA1075
V2
CANL
SPLIT
CANH
60 Ω
60 Ω
R
R
GND
V
SPLIT
= 0.5 V
CC
in normal mode;
otherwise floating
015aaa12
0
P1-P3P4-P6P7-P9P10-P12P13-P15P16-P18P19-P21P22-P24P25-P27P28-P30P31-P33P34-P36P37-P39P40-P42P43-P45P46-P48P49-P51P52-P53

UJA1075TW/3V3,112

Mfr. #:
Buy UJA1075TW/3V3,112
Manufacturer:
NXP Semiconductors
Description:
IC SBC CAN/LIN HS 3.3V 32HTSSOP
Lifecycle:
New from this manufacturer.
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