UJA1075_2 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2010. All rights reserved.
Product data sheet Rev. 02 — 27 May 2010 40 of 53
NXP Semiconductors
UJA1075
High-speed CAN/LIN core system basis chip
10. Dynamic characteristics
Table 11. Dynamic characteristics
T
vj
=
−
40 °C to +150
°
C; V
BAT
= 4.5 V to 28 V; V
BAT
> V
V1
; V
BAT
> V
V2
; R
LIN
=500
Ω
; R
(CANH- CANL)
= 45
Ω
to 65
Ω
; all voltages
are defined with respect to ground; positive currents flow in the IC; typical values are given at V
BAT
= 14 V; unless otherwise
specified.
Symbol Parameter Conditions Min Typ Max Unit
Voltage source; pin V1
t
d(uvd)
undervoltage detection
delay time
V
V1
falling; dV
V1
/dt = 0.1 V/μs7-23μs
t
det(CL)L
LOW-level clamping
detection time
V
V1
<0.9V
O(V1)nom
; V1 active 95 - 140 ms
Voltage source; pin V2
t
d(uvd)
undervoltage detection
delay time
V
V2
falling, dV
V2
/dt = 0.1 V/us 7 - 23 μs
Serial peripheral interface timing; pins SCSN, SCK, SDI and SDO
t
cy(clk)
clock cycle time V
V1
= 2.97 V to 5.5 V 320 - - ns
t
SPILEAD
SPI enable lead time V
V1
= 2.97 V to 5.5 V; clock is LOW
when SPI select falls
110 - - ns
t
SPILAG
SPI enable lag time V
V1
= 2.97 V to 5.5 V; clock is LOW
when SPI select rises
140 - - ns
t
clk(H)
clock HIGH time V
V1
= 2.97 V to 5.5 V 160 - - ns
t
clk(L)
clock LOW time V
V1
= 2.97 V to 5.5 V 160 - - ns
t
su(D)
data input set-up time V
V1
= 2.97 V to 5.5 V 0 - - ns
t
h(D)
data input hold time V
V1
= 2.97 V to 5.5 V 80 - - ns
t
v(Q)
data output valid time pin SDO; V
V1
= 2.97 V to 5.5 V
C
L
= 100 pF
--110ns
t
WH(S)
chip select pulse width HIGH V
V1
= 2.97 V to 5.5 V 20 - - ns
Reset output; pin RSTN
t
w(rst)
reset pulse width long; I
pu(RSTN)
< 100 μA; no pull-up 20 - 25 ms
short; R
pu(RSTN)
= 900 Ω to 1100 Ω 3.6 - 5 ms
t
det(CL)L
LOW-level clamping
detection time
RSTN driven HIGH internally but RSTN
remains LOW
95 - 140 ms
t
fltr
filter time 7 - 18 μs
Watchdog off input; pin WDOFF
t
fltr
filter time 0.9 - 2.3 ms
Wake input; pin WAKE1, WAKE2
t
wake
wake-up time 10 - 40 μs
t
d(po)
power-on delay time 113 - 278 μs
CAN transceiver timing; pins CANH, CANL, TXDC and RXDC
t
d(TXDCH-RXDCH)
delay time from TXDC HIGH
to RXDC HIGH
50 % V
TXDC
to 50 % V
RXDC
V
V2
= 4.5 V to 5.5 V
R
(CANH-CANL)
= 60 Ω
C
(CANH-CANL)
= 100 pF; C
RXDC
= 15 pF
f
TXDC
= 250 kHz
60 - 235 ns
