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XR16L2552IJ-F

P1-P3P4-P6P7-P9P10-P12P13-P15P16-P18P19-P21P22-P24P25-P27P28-P30P31-P33P34-P36P37-P39P40-P42P43-P45
XR16L2552
10
2.25V TO 5.5V DUART WITH 16-BYTE FIFO REV. 1.1.2
The on-chip oscillator is designed to use an industry standard microprocessor crystal (parallel resonant,
fundamental frequency with 10-22 pF capacitance load, ESR of 20-120 ohms and 100ppm frequency
tolerance) connected externally between the XTAL1 and XTAL2 pins (see Figure 2), with an external 500kΩ to
1 MΩ resistor across it. Alternatively, an external clock can be connected to the XTAL1 pin to clock the internal
baud rate generator for standard or custom rates. Typical oscillator connections are shown in Figure 4. For
further reading on oscillator circuit please see application note DAN108 on EXAR’s web site.
2.11 Programmable Baud Rate Generator
A single baud rate generator is provided for the transmitter and receiver, allowing independent TX/RX channel
control. The programmable Baud Rate Generator is capable of operating with a crystal frequency of up to 24
MHz. However, with an external clock input on XTAL1 pin and a 2K ohms pull-up resistor on XTAL2 pin (as
shown in Figure 5) it can extend its operation up to 64 MHz (4Mbps serial data rate) at room temperature and
5.0V.
F
IGURE 4. TYPICAL OSCILLATOR CONNECTIONS
FIGURE 5. EXTERNAL CLOCK CONNECTION FOR EXTENDED DATA RATE
C1
22-47 pF
C2
22-47 pF
Y1
1.8432 MHz
to
24 MHz
R1
0-120 Ω
(Optional)
R2
500 KΩ − 1 MΩ
XTAL1 XTAL2
2K
XTAL1
XTAL2
R1
VCC
External Clock
vcc
gnd
XR16L2552
11
REV. 1.1.2 2.25V TO 5.5V DUART WITH 16-BYTE FIFO
To obtain maximum data rate, it is necessary to use full rail swing on the clock input. See external clock
operating frequency over power supply voltage chart in Figure 6.
The L2552 divides the basic external clock by 16. The basic 16X clock provides table rates to support standard
and custom applications using the same system design. The Baud Rate Generator divides this 16X clock by
any divisor from 1 to 2
16
-1. The rate table is configured via the DLL and DLM internal register functions.
Customized Baud Rates can be achieved by selecting the proper divisor values for the MSB and LSB sections
of baud rate generator.
Table 5 shows the standard data rates available with a 14.7456 MHz crystal or external clock at 16X sampling
rate. When using a non-standard frequency crystal or external clock, the divisor value can be calculated for
DLL/DLM with the following equation.
F
IGURE 6. OPERATING FREQUENCY CHART. REQUIRES A 2K OHMS PULL-UP RESIS-
TOR ON XTAL2 PIN TO INCREASE OPERATING SPEED
divisor (decimal) = (XTAL1 or External clock frequency ) / (serial data rate x 16)
TABLE 5: TYPICAL DATA RATES WITH A 14.7456 MHZ CRYSTAL OR EXTERNAL CLOCK
OUTPUT Data Rate
MCR Bit-7=0
DIVISOR FOR 16x
Clock (Decimal)
DIVISOR FOR 16x
Clock (HEX)
DLM PROGRAM
V
ALUE (HEX)
DLL P
ROGRAM
V
ALUE (HEX)
D
ATA RATE
ERROR (%)
400 2304 900 09 00 0
2400 384 180 01 80 0
4800 192 C0 00 C0 0
9600 96 60 00 60 0
19.2k 48 30 00 30 0
38.4k 24 18 00 18 0
76.8k 12 0C 00 0C 0
60
50
40
30
3.0 4.5 5.53.5
4.0 5.0
Suppy Voltage
XTAL1 External Clock Frequency in MHz.
70
80
85
o
C
25
o
C
-40
o
C
Operating frequency for XR16L2552
with external clock and a 2K ohms
pull-up resistor on XTAL2 pin.
XR16L2552
12
2.25V TO 5.5V DUART WITH 16-BYTE FIFO REV. 1.1.2
2.12 Transmitter
The transmitter section comprises of an 8-bit Transmit Shift Register (TSR) and 16 bytes of FIFO which
includes a byte-wide Transmit Holding Register (THR). TSR shifts out every data bit with the 16X internal
clock. A bit time is 16 clock periods. The transmitter sends the start-bit followed by the number of data bits,
inserts the proper parity-bit if enabled, and adds the stop-bit(s). The status of the FIFO and TSR are reported in
the Line Status Register (LSR bit-5 and bit-6).
2.12.1 Transmit Holding Register (THR) - Write Only
The transmit holding register is an 8-bit register providing a data interface to the host processor. The host
writes transmit data byte to the THR to be converted into a serial data stream including start-bit, data bits,
parity-bit and stop-bit(s). The least-significant-bit (Bit-0) becomes first data bit to go out. The THR is the input
register to the transmit FIFO of 16 bytes when FIFO operation is enabled by FCR bit-0. Every time a write
operation is made to the THR, the FIFO data pointer is automatically bumped to the next sequential data
location.
2.12.2 Transmitter Operation in non-FIFO Mode
The host loads transmit data to THR one character at a time. The THR empty flag (LSR bit-5) is set when the
data byte is transferred to TSR. THR flag can generate a transmit empty interrupt (ISR bit-1) when it is enabled
by IER bit-1. The TSR flag (LSR bit-6) is set when TSR becomes completely empty.
2.12.3 Transmitter Operation in FIFO Mode
The host may fill the transmit FIFO with up to 16 bytes of transmit data. The THR empty flag (LSR bit-5) is set
whenever the FIFO is empty. The THR empty flag can generate a transmit empty interrupt (ISR bit-1) when the
transmit empty interrupt is enabled by IER bit-1. The TSR flag (LSR bit-6) is set when the FIFO and the TSR
become empty.
153.6k 6 06 00 06 0
230.4k 4 04 00 04 0
460.8k 2 02 00 02 0
921.6k 1 01 00 01 0
FIGURE 7. TRANSMITTER OPERATION IN NON-FIFO MODE
TABLE 5: TYPICAL DATA RATES WITH A 14.7456 MHZ CRYSTAL OR EXTERNAL CLOCK
OUTPUT Data Rate
MCR Bit-7=0
DIVISOR FOR 16x
Clock (Decimal)
DIVISOR FOR 16x
Clock (HEX)
DLM PROGRAM
V
ALUE (HEX)
DLL P
ROGRAM
V
ALUE (HEX)
D
ATA RATE
ERROR (%)
Transmit
Holding
Register
(THR)
Transmit Shift Register (TSR)
Data
Byte
L
S
B
M
S
B
THR Interrupt (ISR bit-1)
Enabled by IER bit-1
TXNOFIFO1
16X
Clock
P1-P3P4-P6P7-P9P10-P12P13-P15P16-P18P19-P21P22-P24P25-P27P28-P30P31-P33P34-P36P37-P39P40-P42P43-P45

XR16L2552IJ-F

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Manufacturer:
MaxLinear
Description:
UART Interface IC UART
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