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XR16L2552IJ-F

P1-P3P4-P6P7-P9P10-P12P13-P15P16-P18P19-P21P22-P24P25-P27P28-P30P31-P33P34-P36P37-P39P40-P42P43-P45
XR16L2552
40
2.25V TO 5.5V DUART WITH 16-BYTE FIFO REV. 1.1.2
FIGURE 18. RECEIVE READY & INTERRUPT TIMING [NON-FIFO MODE] FOR CHANNELS A & B
F
IGURE 19. TRANSMIT READY & INTERRUPT TIMING [NON-FIFO MODE] FOR CHANNELS A & B
RX
RXRDY#
IOR#
INT
D0:D7
Start
Bit
D0:D7
Stop
Bit
D0:D7
T
SSR
1 Byte
in RHR
Active
Data
Ready
Active
Data
Ready
Active
Data
Ready
1 Byte
in RHR
1 Byte
in RHR
T
SSR
T
SSR
RXNFM
T
RR
T
RR
T
RR
T
SSR
T
SSR
T
SSR
(Reading data
out of RHR)
TX
TXRDY#
IOW#
INT*
D0:D7
Start
Bit
D0:D7
Stop
Bit
D0:D7
T
WT
TXNonFIFO
T
WT
T
WT
T
WRI
T
WRI
T
WRI
T
SRT
T
SRT
T
SRT
*INT is cleared when the ISR is read or when data is loaded into the THR.
ISR is read ISR is readISR is read
(Loading data
into THR)
(Unloading)
IER[1]
enabled
XR16L2552
41
REV. 1.1.2 2.25V TO 5.5V DUART WITH 16-BYTE FIFO
FIGURE 20. RECEIVE READY & INTERRUPT TIMING [FIFO MODE, DMA DISABLED] FOR CHANNELS A & B
F
IGURE 21. RECEIVE READY & INTERRUPT TIMING [FIFO MODE, DMA ENABLED] FOR CHANNELS A & B
RX
RXRDY#
IOR#
INT
D0:D7
S
T
SSR
RXINTDMA#
RX FIFO fills up to RX
Trigger Level or RX Data
Timeout
RX FIFO drops
below RX
Trigger Level
FIFO
Empties
First Byte is
Received in
RX FIFO
D0:D7
S
D0:D7T D0:D7
S
D0:D7
S
T D0:D7
S
T
T
D0:D7
S
T
Start
Bit
Stop
Bit
T
RR
T
RRI
T
SSI
(Reading data out
of RX FIFO)
RX
RXRDY#
IOR#
INT
D0:D7
S
T
SSR
RXFIFODMA
RX FIFO fills up to RX
Trigger Level or RX Data
Timeout
RX FIFO drops
below RX
Trigger Level
FIFO
Empties
D0:D7
S
D0:D7T D0:D7
S
D0:D7
S
T D0:D7
S
T
T
D0:D7
S
T
Start
Bit
Stop
Bit
T
RR
T
RRI
T
SSI
(Reading data out
of RX FIFO)
XR16L2552
42
2.25V TO 5.5V DUART WITH 16-BYTE FIFO REV. 1.1.2
FIGURE 22. TRANSMIT READY & INTERRUPT TIMING [FIFO MODE, DMA MODE DISABLED] FOR CHANNELS A & B
F
IGURE 23. TRANSMIT READY & INTERRUPT TIMING [FIFO MODE, DMA MODE ENABLED] FOR CHANNELS A & B
TX
TXRDY#
IOW#
INT*
TXDMA#
D0:D7
S
D0:D7T D0:D7
S
D0:D7
S
T D0:D7
S
T
T
D0:D7
S
T
Start
Bit
Stop
Bit
T
WRI
(Unloading)
(Loading data
into FIFO)
Last Data Byte
Transmitted
TX FIFO no
longer empty
Data in
TX FIFO
TX FIFO
Empty
T
WT
T
SRT
TX FIFO
Empty
T
TS
T
SI
ISR is read
IER[1]
enabled
*INT is cleared when the ISR is read or when there is at least one character in the FIFO.
TX
TXRDY#
IOW#
INT*
TXDMA
D0:D7
S
D0:D7T D0:D7
S
D0:D7
S
T D0:D7
S
T
T
D0:D7
S
T
Start
Bit
Stop
Bit
T
WRI
(Unloading)
(Loading data
into FIFO)
Last Data Byte
Transmitted
TX FIFO no
longer empty
TX FIFO
Empty
TX FIFO
Empty
T
TS
T
SI
ISR is read
IER[1]
enabled
*INT is cleared when the ISR is read or when there is at least one character in the FIFO.
At least 1
empty location
in FIFO
T
SRT
TX FIFO
Full
T
WT
P1-P3P4-P6P7-P9P10-P12P13-P15P16-P18P19-P21P22-P24P25-P27P28-P30P31-P33P34-P36P37-P39P40-P42P43-P45

XR16L2552IJ-F

Mfr. #:
Buy XR16L2552IJ-F
Manufacturer:
MaxLinear
Description:
UART Interface IC UART
Lifecycle:
New from this manufacturer.
Delivery:
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