XR16L2552
34
2.25V TO 5.5V DUART WITH 16-BYTE FIFO REV. 1.1.2
EFR[6]: Auto RTS Flow Control Enable
RTS# output may be used for hardware flow control by setting EFR bit-6 to logic 1. When Auto RTS is
selected, an interrupt will be generated when the receive FIFO is filled to the programmed trigger level and
RTS de-asserts to a logic 1 at the next upper trigger level. RTS# will return to a logic 0 when FIFO data falls
below the next lower trigger level. The RTS# output must be asserted (logic 0) before the auto RTS can take
effect. RTS# pin will function as a general purpose output when hardware flow control is disabled.
Logic 0 = Automatic RTS flow control is disabled (default).
Logic 1 = Enable Automatic RTS flow control.
EFR[7]: Auto CTS Flow Control Enable
Automatic CTS Flow Control.
Logic 0 = Automatic CTS flow control is disabled (default).
Logic 1 = Enable Automatic CTS flow control. Data transmission stops when CTS# input de-asserts to logic
1. Data transmission resumes when CTS# returns to a logic 0.
4.17 Software Flow Control Registers (XOFF1, XOFF2, XON1, XON2) - Read/Write
These registers are used as the programmable software flow control characters XOFF1, XOFF2, XON1, and
XON2. For more details, see Table 6.
XR16L2552
35
REV. 1.1.2 2.25V TO 5.5V DUART WITH 16-BYTE FIFO
TABLE 13: UART RESET CONDITIONS FOR CHANNELS A AND B
REGISTERS RESET STATE
DLL Bits 7-0 = 0xXX
DLM Bits 7-0 = 0xXX
AFR Bits 7-0 = 0x00
RHR Bits 7-0 = 0xXX
THR Bits 7-0 = 0xXX
IER Bits 7-0 = 0x00
FCR Bits 7-0 = 0x00
ISR Bits 7-0 = 0x01
LCR Bits 7-0 = 0x00
MCR Bits 7-0 = 0x00
LSR Bits 7-0 = 0x60
MSR Bits 3-0 = Logic 0
Bits 7-4 = Logic levels of the inputs inverted
SPR Bits 7-0 = 0xFF
EFR Bits 7-0 = 0x00
XON1 Bits 7-0 = 0x00
XON2 Bits 7-0 = 0x00
XOFF1 Bits 7-0 = 0x00
XOFF2 Bits 7-0 = 0x00
I/O SIGNALS RESET STATE
TX Logic 1
MF# Logic 1
RTS# Logic 1
DTR# Logic 1
TXRDY# Logic 0
INT Logic 0
TYPICAL PACKAGE THERMAL RESISTANCE DATA (MARGIN OF ERROR: ± 15%)
Thermal Resistance (48-TQFP)
theta-ja =59
o
C/W, theta-jc = 16
o
C/W
Thermal Resistance (44-PLCC)
theta-ja = 50
o
C/W, theta-jc = 21
o
C/W
XR16L2552
36
2.25V TO 5.5V DUART WITH 16-BYTE FIFO REV. 1.1.2
ELECTRICAL CHARACTERISTICS
Test 1: The following inputs must remain steady at VCC or GND state to minimize Sleep current: A0-A2, D0-
D7, IOR#, IOW#, CS#, CHSEL, and all modem inputs. Also, RXA and RXB inputs must idle at logic 1 state
while asleep. Floating inputs will result in sleep currents in the mA range. For PowerSave feature that isolates
address, data and control signals, please see the XR16L2551 datasheet.
ABSOLUTE MAXIMUM RATINGS
Power Supply Range 7 Volts
Voltage at Any Pin GND-0.3 V to +5.5 V
Operating Temperature
-40
o
to +85
o
C
Storage Temperature
-65
o
to +150
o
C
Package Dissipation 500 mW
DC ELECTRICAL CHARACTERISTICS
Unless otherwise noted: 40
o
to +85
o
C for industrial grade package, Vcc is 2.25 to 5.5V
SYMBOL PARAMETER
LIMITS
2.5V
M
IN MAX
LIMITS
3.3V
M
IN MAX
LIMITS
5.0V
M
IN MAX
UNITS CONDITIONS
V
ILCK
Clock Input Low Level -0.3 0.2 -0.3 0.6 -0.5 0.6 V
V
IHCK
Clock Input High Level 2.0 5.5 2.4 5.5 3.0 5.5 V
V
IL
Input Low Voltage -0.3 0.6 -0.3 0.8 -0.5 0.8 V
V
IH
Input High Voltage 2.0 5.5 2.0 5.5 2.2 5.5 V
V
OL
Output Low Voltage
0.4
0.4
0.4 V
V
V
I
OL
= 6 mA
I
OL
= 4 mA
I
OL
= 2 mA
V
OH
Output High Voltage
1.8
2.0
2.4 V
V
V
I
OH
= -6 mA
I
OH
= -1 mA
I
OH
= -400 uA
I
IL
Input Low Leakage Current ±10 ±10 ±10 uA
I
IH
Input High Leakage Current ±10 ±10 ±10 uA
C
IN
Input Pin Capacitance 5 5 5 pF
I
CC
Power Supply Current 1 1.3 3 mA
I
SLEEP
Sleep Current 6 15 30 uA See Test 1

XR16L2552IJ-F

Mfr. #:
Manufacturer:
MaxLinear
Description:
UART Interface IC UART
Lifecycle:
New from this manufacturer.
Delivery:
DHL FedEx Ups TNT EMS
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