XR16L2552
6
2.25V TO 5.5V DUART WITH 16-BYTE FIFO REV. 1.1.2
Pin type: I=Input, O=Output, I/O= Input/output, OD=Output Open Drain.
1.0 PRODUCT DESCRIPTION
The XR16L2552 (L2552) provides serial asynchronous receive data synchronization, parallel-to-serial and
serial-to-parallel data conversions for both the transmitter and receiver sections. These functions are
necessary for converting the serial data stream into parallel data that is required with digital data systems.
Synchronization for the serial data stream is accomplished by adding start and stop bits to the transmit data to
form a data character (character orientated protocol). Data integrity is ensured by attaching a parity bit to the
data character. The parity bit is checked by the receiver for any transmission bit errors. The electronic circuitry
to provide all these functions is fairly complex especially when manufactured on a single integrated silicon
chip. The L2552 represents such an integration with greatly enhanced features. The L2552 is fabricated with
an advanced CMOS process.
Transmit and Receive FIFOs (16 Bytes each)
The L2552 is an upward solution that provides a dual UART capability with 16 bytes of transmit and receive
FIFO memory, instead of none in the 16C2450. The L2552 is designed to work with low voltage supplies and
high performance data communication systems, that require fast data processing time. Increased performance
is realized in the L2552 by the transmit and receive FIFO’s. This allows the external processor to handle more
networking tasks within a given time. For example, the ST16C2450 without a receive FIFO, will require
unloading of the RHR in 93 microseconds (This example uses a character length of 11 bits, including start/stop
bits at 115.2 Kbps). This means the external CPU will have to service the receive FIFO less than every 100
microseconds. However with the 16 byte FIFO in the L2552, the data buffer will not require unloading/loading
for 1.53 ms. This increases the service interval giving the external CPU additional time for other applications
and reducing the overall UART interrupt servicing time. In addition, the 4 selectable receive FIFO trigger
interrupt levels is uniquely provided for maximum data throughput performance especially when operating in a
multi-channel environment. The FIFO memory greatly reduces the bandwidth requirement of the external
controlling CPU, increases performance, and reduces power consumption.
Enhanced Features
The XR16L2552 integrates the functions of 2 enhanced 16C550 Universal Asynchronous Receiver and
Transmitter (UART). Each UART is independently controlled having its own set of device configuration
registers. The configuration registers set is 16550 UART compatible for control, status and data transfer.
Additionally, each UART channel has automatic RTS/CTS hardware flow control, automatic Xon/Xoff and
special character software flow control, infrared encoder and decoder (IrDA ver 1.0), programmable baud rate
generator with a prescaler of divide by 1 or 4, and data rate up to 4 Mbps at 5V.
Data Rate
The L2552 is capable of operation up to 3.125 Mbps with a 50 MHz external clock. With a crystal or external
clock input of 14.7456 MHz the user can select data rates up to 921.6 Kbps.
The rich feature set of the L2552 is available through internal registers. Selectable receive FIFO trigger levels,
selectable TX and RX baud rates, and modem interface controls are all standard features. Following a power
on reset or an external reset, the L2552 is software compatible with the 16L2752 and 16C2852.
NC 19, 37 - - Not Connected Internally.
Pin Description
NAME
48-TQFP
P
IN#
44-PLCC
P
IN #
TYPE DESCRIPTION
