XR16L2552IJ-F Datasheet XR16L2552IM-F, XR16L2552IJTR-F, XR16L2552IMTR-F | P7-P9

XR16L2552

REV. 1.1.2 2.25V TO 5.5V DUART WITH 16-BYTE FIFO

2.0 FUNCTIONAL DESCRIPTIONS

2.1 CPU Interface

The CPU interface is 8 data bits wide with 3 address lines and control signals to execute data bus read and

write transactions. The L2552 data interface supports the Intel compatible types of CPUs and it is compatible

to the industry standard 16C550 UART. No clock (oscillator nor external clock) is required to operate a data

bus transaction. Each bus cycle is asynchronous using CS#, IOR# and IOW# signals. Both UART channels

share the same data bus for host operations. The data bus interconnections are shown in Figure 3.

2.2 5-Volt Tolerant Inputs

The L2552 can accept up to 5V inputs even when operating at 3.3V or 2.5V. But note that if the L2552 is

operating at 2.5V, its V

may not be high enough to meet the requirements of the V

of a CPU or a serial

transceiver that is operating at 5V.

2.3 Device Reset

The RESET input resets the internal registers and the serial interface outputs in both channels to their default

state (see the Table 13). An active high pulse of longer than 40 ns duration will be required to activate the

reset function in the device.

2.4 Device Identification and Revision

The L2552 provides a Device Identification code and a Device Revision code to distinguish the part from other

devices and revisions. To read the identification code from the part, it is required to set the baud rate generator

registers DLL and DLM both to 0x00. Now reading the content of the DLM will provide 0x02 to indicate L2552

and reading the content of DLL will provide the revision of the part; for example, a reading of 0x01 means

revision A.

IGURE 3. XR16L2552 DATA BUS INTERCONNECTIONS

VCC

(OP2A#)

DSRA#

CTSA#

RTSA#

DTRA#

RXA

TXA

RIA#

CDA#

(OP2B#)

DSRB#

CTSB#

RTSB#

DTRB#

RXB

TXB

RIB#

CDB#

GND

UART_CS#

UART_CHSEL

IOR#

IOW#

CS#

CHSEL

IOR#

IOW#

UART

Channel A

UART

Channel B

UART_INTB

UART_INTA

INTB

INTA

(RXRDYA#)

TXRDYA#

(RXRDYA#)

TXRDYA#

(RXRDYB#)

TXRDYB#

(RXRDYB#)

TXRDYB#

UART_RESET RESET

RS-232 Serial Interface

(BAUDOUTB#)

(BAUDOUTA#)

Pins in parentheses become available through the MF# pin. MF# A/B becomes RXRDY# A/B when AFR[2:1] = '10'. MF# A/B becomes OP2# A/B

when AFR[2:1] = '00'. MF# A/B becomes BAUDOUT# A/B when AFR[1:0] = '01'. RXRDY# pins available on 48-TQFP package.

XR16L2552

2.25V TO 5.5V DUART WITH 16-BYTE FIFO REV. 1.1.2

2.5 Channel A and B Selection

The UART provides the user with the capability to bi-directionally transfer information between an external

CPU and an external serial communication device. A logic 0 on chip select pin (CS#) allows the user to select

the UART and then using the channel select (CHSEL) pin, the user can select channel A or B to configure,

send transmit data and/or unload receive data to/from the UART. Individual channel select functions are shown

in Table 1.

2.6 Channel A and B Internal Registers

Each UART channel in the L2552 has a set of enhanced registers for controlling, monitoring and data loading

and unloading. The configuration register set is compatible to those already available in the standard single

16C550 and dual ST16C2550. These registers function as data holding registers (THR/RHR), interrupt status

and control registers (ISR/IER), a FIFO control register (FCR), receive line status and control registers (LSR/

LCR), modem status and control registers (MSR/MCR), programmable data rate (clock) divisor registers (DLL/

DLM), and a user accessible scratchpad register (SPR).

Beyond the general 16C2550 features and capabilities, the L2552 offers enhanced feature registers (AFR,

EFR, Xon/Xoff 1, Xon/Xoff 2) that provide automatic RTS and CTS hardware flow control, automatic Xon/Xoff

software flow control, and simultaneous writes to both channels. All the register functions are discussed in full

detail later in “UART INTERNAL REGISTERS” .

2.7 Simultaneous Write to Channel A and B

During a write mode cycle, the setting of Alternate Function Register (AFR) bit-0 to a logic 1 will override the

CHSEL selection and allows a simultaneous write to both UART channel sections. This functional capability

allow the registers in both UART channels to be modified concurrently, saving individual channel initialization

time. Caution should be exercised, however, when using this capability. Any in-process serial data transfer

may be disrupted by changing an active channel’s mode.

2.8 DMA Mode

The device does not support direct memory access. The DMA Mode (a legacy term) in this document doesn’t

mean “direct memory access” but refers to data block transfer operation. The DMA mode affects the state of

the RXRDY# A/B (MF# A/B becomes RXRDY# A/B output when AFR[2:1] = ‘10’) and TXRDY# A/B output

pins. The transmit and receive FIFO trigger levels provide additional flexibility to the user for block mode

operation. The LSR bits 5-6 provide an indication when the transmitter is empty or has an empty location(s) for

more data. The user can optionally operate the transmit and receive FIFO in the DMA mode (FCR bit-3=1).

When the transmit and receive FIFO are enabled and the DMA mode is disabled (FCR bit-3 = 0), the L2552 is

placed in single-character mode for data transmit or receive operation. When DMA mode is enabled (FCR bit-

3 = 1), the user takes advantage of block mode operation by loading or unloading the FIFO in a block

sequence determined by the programmed trigger level. The following table show their behavior. Also see

Figure 18 through Figure 23.

ABLE 1: CHANNEL A AND B SELECT

CS# CHSEL FUNCTION

1 X UART de-selected

0 1 Channel A selected

0 0 Channel B selected

XR16L2552

REV. 1.1.2 2.25V TO 5.5V DUART WITH 16-BYTE FIFO

2.9 INTA and INTB Ouputs

The INTA and INTB interrupt outputs change according to the operating mode and enahnced features setup.

Table 3 and Table 4 summarize the operating behavior for the transmitter and receiver. Also see Figure 18

through Figure 23.

2.10 Crystal Oscillator or External Clock Input

The L2552 includes an on-chip oscillator (XTAL1 and XTAL2) to produce a clock for both UART sections in the

device. The CPU data bus does not require this clock for bus operation. The crystal oscillator provides a

system clock to the Baud Rate Generators (BRG) section found in each of the UART. XTAL1 is the input to the

oscillator or external clock buffer input with XTAL2 pin being the output. For programming details, see

“Programmable Baud Rate Generator.”

ABLE 2: TXRDY# AND RXRDY# OUTPUTS IN FIFO AND DMA MODE

PINS

FCR BIT-0=0

(FIFO D

ISABLED)

FCR B

IT-0=1 (FIFO ENABLED)

FCR Bit-3 = 0

(DMA Mode Disabled)

FCR Bit-3 = 1

(DMA Mode Enabled)

RXRDY# A/B

0 = 1 byte.

1 = no data.

0 = at least 1 byte in FIFO

1 = FIFO empty.

1 to 0 transition when FIFO reaches the trigger

level, or timeout occurs.

0 to 1 transition when FIFO empties.

TXRDY# A/B

0 = THR empty.

1 = byte in THR.

0 = FIFO empty.

1 = at least 1 byte in FIFO.

0 = FIFO has at least 1 empty location.

1 = FIFO is full.

TABLE 3: INTA AND INTB PINS OPERATION FOR TRANSMITTER

FCR BIT-0 = 0

(FIFO DISABLED)

FCR BIT-0 = 1

(FIFO ENABLED)

INTA/B Pin 0 = a byte in THR

1 = THR empty

0 = at least 1 byte in FIFO

1 = FIFO empty

TABLE 4: INTA AND INTB PIN OPERATION FOR RECEIVER

FCR BIT-0 = 0

(FIFO D

ISABLED)

FCR B

IT-0 = 1

(FIFO E

NABLED)

INTA/B Pin 0 = no data

1 = 1 byte

0 = FIFO below trigger level

1 = FIFO above trigger level

P1-P3 P4-P6 P7-P9 P10-P12 P13-P15 P16-P18 P19-P21 P22-P24 P25-P27 P28-P30 P31-P33 P34-P36 P37-P39 P40-P42 P43-P45

XR16L2552IJ-F

Mfr. #:

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Manufacturer:

MaxLinear

Description:

UART Interface IC UART

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XR16L2552IJ-F

XR16L2552IJ-F

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