Cyclone V Device Overview
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CV-51001 | 2018.05.07
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Contents
Cyclone V Device Overview................................................................................................. 3
Key Advantages of Cyclone V Devices............................................................................. 3
Summary of Cyclone V Features.....................................................................................4
Cyclone V Device Variants and Packages......................................................................... 5
Cyclone V E........................................................................................................5
Cyclone V GX..................................................................................................... 7
Cyclone V GT......................................................................................................9
Cyclone V SE.................................................................................................... 12
Cyclone V SX....................................................................................................14
Cyclone V ST.................................................................................................... 15
I/O Vertical Migration for Cyclone V Devices...................................................................18
Adaptive Logic Module................................................................................................ 18
Variable-Precision DSP Block........................................................................................19
Embedded Memory Blocks........................................................................................... 21
Types of Embedded Memory............................................................................... 21
Embedded Memory Capacity in Cyclone V Devices................................................. 21
Embedded Memory Configurations.......................................................................22
Clock Networks and PLL Clock Sources.......................................................................... 22
FPGA General Purpose I/O...........................................................................................23
PCIe Gen1 and Gen2 Hard IP....................................................................................... 24
External Memory Interface.......................................................................................... 24
Hard and Soft Memory Controllers....................................................................... 24
External Memory Performance............................................................................ 25
HPS External Memory Performance......................................................................25
Low-Power Serial Transceivers......................................................................................25
Transceiver Channels......................................................................................... 25
PMA Features................................................................................................... 26
PCS Features....................................................................................................27
SoC with HPS.............................................................................................................28
HPS Features....................................................................................................28
FPGA Configuration and Processor Booting............................................................30
Hardware and Software Development.................................................................. 31
Dynamic and Partial Reconfiguration............................................................................. 31
Dynamic Reconfiguration....................................................................................31
Partial Reconfiguration....................................................................................... 31
Enhanced Configuration and Configuration via Protocol....................................................32
Power Management.................................................................................................... 33
Document Revision History for Cyclone V Device Overview...............................................33
Contents
Cyclone V Device Overview
2
Cyclone V Device Overview
The Cyclone
®
V devices are designed to simultaneously accommodate the shrinking
power consumption, cost, and time-to-market requirements; and the increasing
bandwidth requirements for high-volume and cost-sensitive applications.
Enhanced with integrated transceivers and hard memory controllers, the Cyclone V
devices are suitable for applications in the industrial, wireless and wireline, military,
and automotive markets.
Related Information
Cyclone V Device Handbook: Known Issues
Lists the planned updates to the Cyclone V Device Handbook chapters.
Key Advantages of Cyclone V Devices
Table 1. Key Advantages of the Cyclone V Device Family
Advantage Supporting Feature
Lower power consumption Built on TSMC's 28 nm low-power (28LP) process technology and includes an
abundance of hard intellectual property (IP) blocks
Up to 40% lower power consumption than the previous generation device
Improved logic integration and
differentiation capabilities
8-input adaptive logic module (ALM)
Up to 13.59 megabits (Mb) of embedded memory
Variable-precision digital signal processing (DSP) blocks
Increased bandwidth capacity 3.125 gigabits per second (Gbps) and 6.144 Gbps transceivers
Hard memory controllers
Hard processor system (HPS)
with integrated Arm* Cortex*-A9
MPCore* processor
Tight integration of a dual-core Arm Cortex-A9 MPCore processor, hard IP, and an
FPGA in a single Cyclone V system-on-a-chip (SoC)
Supports over 128 Gbps peak bandwidth with integrated data coherency between
the processor and the FPGA fabric
Lowest system cost Requires only two core voltages to operate
Available in low-cost wirebond packaging
Includes innovative features such as Configuration via Protocol (CvP) and partial
reconfiguration
CV-51001 | 2018.05.07
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and Stratix words and logos are trademarks of Intel Corporation or its subsidiaries in the U.S. and/or other
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accordance with Intel's standard warranty, but reserves the right to make changes to any products and services
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customers are advised to obtain the latest version of device specifications before relying on any published
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FPGA - Field Programmable Gate Array FPGA - Cyclone V GX 5648 LABs 224 IOs
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