5CGXFC7C6U19C7N Datasheet 5CEBA4U15I7N, 5CEFA9F23I7N, 5CGXFC9D6F27I7N | P13-P15

Maximum Resources

Table 10. Maximum Resource Counts for Cyclone V SE Devices

Resource Member Code

A2 A4 A5 A6

Logic Elements (LE) (K) 25 40 85 110

ALM 9,430 15,880 32,070 41,910

Memory (Kb) M10K 1,400 2,700 3,970 5,570

MLAB 138 231 480 621

Variable-precision DSP Block 36 84 87 112

18 x 18 Multiplier 72 168 174 224

FPGA PLL 5 5 6 6

HPS PLL 3 3 3 3

FPGA GPIO 145 145 288 288

HPS I/O 181 181 181 181

LVDS Transmitter 32 32 72 72

Receiver 37 37 72 72

FPGA Hard Memory Controller 1 1 1 1

HPS Hard Memory Controller 1 1 1 1

Arm Cortex-A9 MPCore Processor Single- or dual-

core

Single- or dual-

core

Single- or dual-core Single- or dual-core

Related Information

True LVDS Buffers in Devices, I/O Features in Cyclone V Devices

Provides the number of LVDS channels in each device package.

Package Plan

Table 11. Package Plan for Cyclone V SE Devices

The HPS I/O counts are the number of I/Os in the HPS and does not correlate with the number of HPS-specific

I/O pins in the FPGA. Each HPS-specific pin in the FPGA may be mapped to several HPS I/Os.

Member Code

U484

(19 mm)

U672

(23 mm)

F896

(31 mm)

FPGA GPIO HPS I/O FPGA GPIO HPS I/O FPGA GPIO HPS I/O

A2 66 151 145 181 — —

A4 66 151 145 181 — —

A5 66 151 145 181 288 181

A6 66 151 145 181 288 181

Cyclone V Device Overview

CV-51001 | 2018.05.07

Cyclone V Device Overview

Cyclone V SX

This section provides the available options, maximum resource counts, and package

plan for the Cyclone V SX devices.

The information in this section is correct at the time of publication. For the latest

information and to get more details, refer to the Product Selector Guide.

Related Information

Product Selector Guide

Provides the latest information about Intel products.

Available Options

Figure 5. Sample Ordering Code and Available Options for Cyclone V SX Devices

The SEU internal scrubbing feature is available for Cyclone V E, GX, SE, and SX devices with the "SC" suffix in

the part number. For device availability and ordering, contact your local Intel sales representatives.

Cyclone V SE and SX low-power devices (L power option) offer 30% static power reduction for devices with

25K LE and 40K LE, and 20% static power reduction for devices with 85K LE and 110K LE.

Family Signature

Embedded Hard IPs

Transceiver Count

Transceiver

Speed Grade

Package Type

Package Code

Operating Temperature

FPGA Fabric

Speed Grade

Optional Suffix

Indicates specific device

options or shipment method

SX : SoC with 3-Gbps transceivers

F : Maximum 2 hard PCIe

controllers and 1 hard

memory controller

5C : Cyclone V

C2 : 25K logic elements

C4 : 40K logic elements

C5 : 85K logic elements

C6 : 110K logic elements

C : 6

D : 9

6 : 3.125 Gbps

F : FineLine BGA (FBGA)

U : Ultra FineLine BGA (UBGA)

FBGA Package Type

31 : 896 pins

UBGA Package Type

23 : 672 pins

C : Commercial (T

= 0° C to 85° C)

I : Industrial (T

= -40° C to 100° C)

A : Automotive (T

= -40° C to 125° C)

6 (fastest)

N : Lead-free packaging

Contact Intel for availability

of leaded options

ES : Engineering sample

C6 D

F 31

Member Code

Family Variant

SC : Internal scrubbing support

Power Option

Omit for standard power

L : Low power

Maximum Resources

Table 12. Maximum Resource Counts for Cyclone V SX Devices

Resource Member Code

C2 C4 C5 C6

Logic Elements (LE) (K) 25 40 85 110

ALM 9,430 15,880 32,070 41,910

Memory (Kb) M10K 1,400 2,700 3,970 5,570

MLAB 138 231 480 621

Variable-precision DSP Block 36 84 87 112

18 x 18 Multiplier 72 168 174 224

FPGA PLL 5 5 6 6

continued...

Cyclone V Device Overview

CV-51001 | 2018.05.07

Cyclone V Device Overview

Resource Member Code

C2 C4 C5 C6

HPS PLL 3 3 3 3

3 Gbps Transceiver 6 6 9 9

FPGA GPIO

(8)

145 145 288 288

HPS I/O 181 181 181 181

LVDS Transmitter 32 32 72 72

Receiver 37 37 72 72

PCIe Hard IP Block 2 2 2

(9)

FPGA Hard Memory Controller 1 1 1 1

HPS Hard Memory Controller 1 1 1 1

Arm Cortex-A9 MPCore Processor Dual-core Dual-core Dual-core Dual-core

Related Information

True LVDS Buffers in Devices, I/O Features in Cyclone V Devices

Provides the number of LVDS channels in each device package.

Package Plan

Table 13. Package Plan for Cyclone V SX Devices

The HPS I/O counts are the number of I/Os in the HPS and does not correlate with the number of HPS-specific

I/O pins in the FPGA. Each HPS-specific pin in the FPGA may be mapped to several HPS I/Os.

Member Code

U672

(23 mm)

F896

(31 mm)

FPGA GPIO HPS I/O XCVR FPGA GPIO HPS I/O XCVR

C2 145 181 6 — — —

C4 145 181 6 — — —

C5 145 181 6 288 181 9

C6 145 181 6 288 181 9

Cyclone V ST

This section provides the available options, maximum resource counts, and package

plan for the Cyclone V ST devices.

The information in this section is correct at the time of publication. For the latest

information and to get more details, refer to the Product Selector Guide.

(8)

The number of GPIOs does not include transceiver I/Os. In the Intel Quartus Prime software,

the number of user I/Os includes transceiver I/Os.

(9)

1 PCIe Hard IP Block in U672 package.

Cyclone V Device Overview

CV-51001 | 2018.05.07

Cyclone V Device Overview

P1-P3 P4-P6 P7-P9 P10-P12 P13-P15 P16-P18 P19-P21 P22-P24 P25-P27 P28-P30 P31-P33 P34-P36 P37-P37

5CGXFC7C6U19C7N

Mfr. #:

Buy 5CGXFC7C6U19C7N

Manufacturer:

Intel / Altera

Description:

FPGA - Field Programmable Gate Array FPGA - Cyclone V GX 5648 LABs 224 IOs

Lifecycle:

New from this manufacturer.

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