AD7708BRUZ-REEL Datasheet AD7718BRZ, AD7718BRUZ, AD7708BRUZ | P25-P27

REV. 0

AD7708/AD7718

–25–

Communications Register (A3, A2, A1, A0 = 0, 0, 0, 0)

The Communications Register is an 8-bit write-only register. All communications to the part must start with a write operation to the

Communications Register. The data written to the Communications Register determines whether the next operation is a read or write

operation, the type of read operation, and on which register this operation takes place. For read or write operations, once the subse-

quent read or write operation to the selected register is complete, the interface returns to where it expects a write operation to the

Communications Register. This is the default state of the interface and, on power-up or after a RESET, the AD7708/AD7718 is in

this default state waiting for a write operation to the Communications Register. In situations where the interface sequence is lost, a

write operation of at least 32 serial clock cycles with DIN high returns the AD7708/AD7718 to this default state by resetting the part.

Table XII outlines the bit designations for the Communications Register. CR0 through CR7 indicate the bit location, CR denoting

the bits are in the Communications Register. CR7 denotes the first bit of the data stream.

7RC6RC5RC4RC3RC2RC1RC0RC

NEW )0(

/R W )0()0(0)0(0)0(3A)0(2A)0(1A)0(0A

Table XII. Communications Register Bit Designations

Bit Bit

Location Mnemonic Description

CR7 WEN Write Enable Bit. A 0 must be written to this bit so the write operation to the Communications Register

actually takes place. If a 1 is written to this bit, the part will not clock on to subsequent bits in the regis

ter. It will stay at this bit location until a 0 is written to this bit. Once a 0 is written to the WEN bit, the

next seven bits will be loaded to the Communications Register.

CR6 R/W A zero in this bit location indicates that the next operation will be a write to a specified register. A one in

this position indicates that the next operation will be a read from the designated register.

CR5 0 A zero must be written to this bit position to ensure correct operation of the AD7708/AD7718.

CR4 0 A zero must be written to this bit position to ensure correct operation of the AD7708/AD7718.

CR3–CR0 A3–A0 Register Address Bits. These address bits are used to select which of the AD7708/AD7718’s registers are

being accessed during this serial interface communication. A3 is the MSB of the three selection bits.

Table XIII. Register Selection Table

A3 A2 A1 A0 Register

0000Communications Register during a Write Operation

0000Status Register during a Read Operation

0001Mode Register

0010ADC Control Register

0011Filter Register

0100ADC Data Register

0101ADC Offset Register

0110ADC Gain Register

0111I/O Control Register

1000Undefined

1001Undefined

1010Undefined

1011Undefined

1100Test 1 Register

1101Test 2 Register

1110Undefined

1111ID Register

REV. 0

–26–

AD7708/AD7718

Status Register (A3, A2, A1, A0 = 0, 0, 0, 0; Power-On-Reset = 00Hex)

The ADC Status Register is an 8-bit read-only register. To access the ADC Status Register, the user must write to the Communica-

tions Register selecting the next operation to be a read and load Bits A3-A0 with 0, 0, 0,0. Table XIV outlines the bit designations

for the Status Register. SR0 through SR7 indicate the bit location, SR denoting the bits are in the Status Register. SR7 denotes the

first bit of the data stream. The number in brackets indicates the power-on/reset default status of that bit.

RS7 6RS5RS4RS3RS2RS1RS0RS

YDR)0()0(0)0(LAC)0(0)0(RRE)0(0)0(0)0(KCOL

Table XIV. Status Register Bit Designations

Bit Bit

Location Mnemonic Description

SR7 RDY Ready Bit for the ADC

Set when data is transferred to the ADC data registers or on completion of calibration cycle. The RDY

bit is cleared automatically a period of time before the data register is updated with a new conversion

result or after the ADC data register has been read. This bit is also cleared by a write to the mode bits to

indicate a conversion or calibration. The RDY pin is the complement of the RDY bit.

SR6 0 Bit is automatically cleared. Reserved for future use

SR5 CAL Calibration Status Bit

Set to indicate completion of calibration. It is set at the same time that the RDY is set high.

Cleared by a write to the mode bits to start another ADC conversion or calibration.

SR4 0 This bit is automatically cleared. Reserved for future use

SR3 ERR ADC Error Bit

Set to indicate that the result written to the ADC data register has been clamped to all zeros or all ones.

After a calibration this bit also flags error conditions that caused the calibration registers not to be

written. Error sources include Overrange.

Cleared by a write to the mode bits to initiate a conversion or calibration.

SR2 0 This bit is automatically cleared. Reserved for future use

SR1 0 This bit is automatically cleared. Reserved for future use

SR0 LOCK PLL Lock Status Bit.

Set if the PLL has locked onto the 32.768 kHz crystal oscillator clock. If the user is worried about

exact sampling frequencies etc., the LOCK bit should be interrogated and the result discarded if the

LOCK bit is zero.

REV. 0

AD7708/AD7718

–27–

Mode Register (A3, A2, A1, A0 = 0, 0, 0, 1; Power-On-Reset = 00Hex)

The Mode Register is an 8-bit register from which data can be read or to which data can be written. This register configures the

operating modes of the AD7708/AD7718. Table XV outlines the bit designations for the Mode Register. MR7 through MR0 indi-

cate the bit location, MR denoting the bits are in the Mode Register. MR7 denotes the first bit of the data stream. The number in

brackets indicates the power-on/reset default status of that bit.

7RM6RM5RM4RM3RM2RM1RM0RM

POHC )0(

)0(FUBGEN)0(LESFER)0(NOCHC)0(DPCSO)0(2DM)0(1DM)0(0DM

Table XV. Mode Register Bit Designations

Bit Bit

Location Mnemonic Description

MR7 CHOP If this bit is cleared, chopping is enabled. When this bit is set chopping is disabled. The default is for

chop enabled.

MR6 NEGBUF This bit controls the operation of the input buffer on the AINCOM input when a channel is config-

ured for pseudo-differential mode of operation. If cleared, the analog negative input (AINCOM) is

unbuffered allowing it to be tied to AGND in single-ended input configuration. If this bit is set the

analog negative input (AINCOM) is buffered, placing a restriction on its common-mode input range.

MR5 REFSEL If this bit is cleared, the reference selected is REFIN1(+) and REFIN1(–) for the active channel. If

this bit is set, the reference selected is REFIN2(+) and REFIN2(–) for the active channel. The con-

tents of the CHCON bit overrides the REFSEL bit. If the ADC is configured in five fully-differential

or 10 pseudo-differential input channel mode, the REFSEL bit setting is irrelevant as only one

reference input is available. V

REF

Select implemented using the REFSEL bit enables the user to

perform both absolute and ratiometric measurements.

MR4 CHCON When cleared the device is configured as an 8-input channel converter, configured as eight pseudo-

differential input channels with respect to AINCOM or four differential input arrangements

with two reference input selection options. When set the device is configured as a 10 pseudo-

differential input or a five differential input channel arrangement with a single reference

input option.

MR3 OSCPD Oscillator Power-Down Bit.

If this bit is set, placing the AD7708/AD7718 in standby mode will stop the crystal oscillator reducing

the power drawn by these parts to a minimum. The oscillator will require 300 ms to begin oscillating

when the ADC is taken out of standby mode. If this bit is cleared, the oscillator is not shut off when

the ADC is put into standby mode and will not require the 300 ms start-up time when the ADC is

taken out of standby.

MR2–MR0 MD2–MD0 ADC Mode Bits.

These bits select the operational mode of the ADC as follows:

MD2 MD1 MD0

0 0 0 Power-Down Mode (Power-On Default)

0 0 1 Idle Mode

In Idle Mode the ADC filter and modulator are held in a reset state although the modulator clocks

are still provided.

0 1 0 Single Conversion Mode

In Single Conversion Mode, a single conversion is performed on the enabled channels. On comple-

tion of the conversion the ADC data registers are updated, the relevant flags in the STATUS register

are written, and idle mode is reentered with the MD2–MD0 being written accordingly to 001.

0 1 1 Continuous Conversion

In continuous conversion mode, the ADC data registers are regularly updated at the selected update

rate (see Filter register).

1 0 0 Internal Zero-Scale Calibration

Internal short automatically connected to the enabled channel(s)

1 0 1 Internal Full-Scale Calibration

External V

REF

is connected automatically to the ADC input for this calibration.

1 1 0 System Zero-Scale Calibration

User should connect system zero-scale input to the channel input pins as selected by CH3–CH0 bits

in the control registers.

1 1 1 System Full-Scale Calibration

User should connect system full-scale input to the channel input pins as selected by CH3–CH0 bits

in the control registers.

P1-P3 P4-P6 P7-P9 P10-P12 P13-P15 P16-P18 P19-P21 P22-P24 P25-P27 P28-P30 P31-P33 P34-P36 P37-P39 P40-P42 P43-P44

AD7708BRUZ-REEL

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Analog to Digital Converters - ADC 16-Bit 8/10-Ch Low Vtg Low Pwr

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AD7708BRUZ-REEL

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