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AD7708BRUZ-REEL

P1-P3P4-P6P7-P9P10-P12P13-P15P16-P18P19-P21P22-P24P25-P27P28-P30P31-P33P34-P36P37-P39P40-P42P43-P44
REV. 0
–7–
AD7708/AD7718
Parameter B Grade Unit Test Conditions
AD7708 (CHOP ENABLED)
Output Update Rate 5.4 Hz min CHOP = 1
105 Hz max 0.732 ms Increments
No Missing Codes
2
16 Bits min 20 Hz Update Rate
Resolution 13 Bits p-p ±20 mV Range, 20 Hz Update Rate
16 Bits p-p ±2.56 V Range, 20 Hz Update Rate
Output Noise and Update Rates See Tables in
ADC Description
Integral Nonlinearity ±15 ppm of FSR max 2 ppm Typical
Offset Error
3
±3 µV typ Calibration is Accurate to ±0.5 LSB
Offset Error Drift vs. Temp
4
10 nV/°C typ
Full-Scale Error
3
±0.75 LSB typ Includes Positive and Negative ERRORS
Gain Drift vs. Temp
4
±0.5 ppm/°C typ
ANALOG INPUTS
Differential Input Full-Scale Voltage ±1.024 × REFIN/GAIN V nom REFIN Refers to Both REFIN1 and
REFIN2. REFIN = REFIN(+) REFIN(–)
GAIN = 1 to 128
Range Matching ±2 µV typ Analog Input = 18 mV
Absolute AIN Voltage Limits AGND + 100 mV V min AIN1–AIN10 and AINCOM with
AV
DD
– 100 mV V max NEGBUF = 1
Absolute AINCOM Voltage Limits AGND – 30 mV V min NEGBUF = 0
AV
DD
+ 30 mV V max
Analog Input Current AIN1–AIN10 and AINCOM with
NEGBUF = 1
DC Input Current
2
±1 nA max
DC Input Current Drift ±5 pA/°C typ
AINCOM Input Current NEGBUF = 0
DC Input Current
2
±125 nA/V typ
DC Bias Current Drift ±2 pA/V/°C typ
Normal-Mode Rejection
2
@ 50 Hz 100 dB min 50 Hz ± 1 Hz, SF Word = 82
@ 60 Hz 94 dB min 60 Hz ± 1 Hz, SF Word = 68
Common-Mode Rejection
@ DC 90 dB min 100 dB typ, Analog Input = 1 V,
Input Range = ±2.56 V
110 dB typ on ±20 mV Range
@ 50 Hz
2
100 dB min 50 Hz ± 1 Hz, 20 Hz Update Rate
@ 60 Hz
2
100 dB min 60 Hz ± 1 Hz, 20 Hz Update Rate
REFERENCE INPUTS (REFIN1 AND REFIN2)
REFIN(+) to REFIN(–) Voltage 2.5 V nom REFIN Refers to Both REFIN1 and
REFIN2
REFIN(+) to REFIN(–) Range
2
1V min
AV
DD
V max
REFIN Common-Mode Range AGND – 30 mV V min
AV
DD
+ 30 mV V max
Reference DC Input Current
2
±0.5 µA/V typ
Reference DC Input Current Drift ±0.01 nA/V/°C typ
Normal-Mode Rejection
2
@ 50 Hz 100 dB min 50 Hz ± 1 Hz, SF Word = 82
@ 60 Hz 100 dB min 60 Hz ± 1 Hz, SF Word = 68
Common-Mode Rejection Input Range = ±2.56 V
@ DC 110 dB typ Analog Input = 1 V
@ 50 Hz 110 dB typ 50 Hz ± 1 Hz, 20 Hz Update Rate
@ 60 Hz 110 dB typ 60 Hz ± 1 Hz, 20 Hz Update Rate
LOGIC INPUTS
5
All Inputs Except SCLK and XTAL1
2
V
INL
, Input Low Voltage 0.8 V max DV
DD
= 5 V
0.4 V max DV
DD
= 3 V
V
INH
, Input High Voltage 2.0 V min DV
DD
= 3 V or 5 V
REV. 0
–8–
AD7718–SPECIFICATIONS
1
(AV
DD
= 2.7 V to 3.6 V or 4.75 V to 5.25 V, DV
DD
= 2.7 V to 3.6 V or 4.75 V to 5.25 V, REFIN(+) =
2.5 V ; REFIN(–) = AGND; AGND = DGND = 0 V; XTAL1/XTAL2 = 32.768 kHz Crystal Input Buffer Enabled. All specifications T
MIN
to T
MAX
unless otherwise noted.)
AD7708
Parameter B Grade Unit Test Conditions
LOGIC INPUTS (Continued)
SCLK Only (Schmitt-Triggered Input)
2
V
T(+)
1.4/2 V min/V max DV
DD
= 5 V
V
T(–)
0.8/1.4 V min/V max DV
DD
= 5 V
V
T(+)
–V
T(–)
0.3/0.85 V min/V max DV
DD
= 5 V
V
T(+)
0.95/2 V min/V max DV
DD
= 3 V
V
T(–)
0.4/1.1 V min/V max DV
DD
= 3 V
V
T(+)
–V
T(–)
0.3/0.85 V min/V max DV
DD
= 3 V
XTAL1 Only
2
V
INL
, Input Low Voltage 0.8 V max DV
DD
= 5 V
V
INH
, Input High Voltage 3.5 V min DV
DD
= 5 V
V
INL
, Input Low Voltage 0.4 V max DV
DD
= 3 V
V
INH
, Input High Voltage 2.5 V min DV
DD
= 3 V
Input Currents ±10 µA max Logic Input = DV
DD
–70 µA max
Logic Input = DGND, Typical –40 µA @ 5 V
and –20 µA at 3 V
Input Capacitance 10 pF typ All Digital Inputs
LOGIC OUTPUTS (Excluding XTAL2)
5
V
OH
, Output High Voltage
2
DV
DD
– 0.6 V min DV
DD
= 3 V, I
SOURCE
= 100 µA
V
OL
, Output Low Voltage
2
0.4 V max DV
DD
= 3 V, I
SINK
= 100 µA
V
OH
, Output High Voltage
2
4V minDV
DD
= 5 V, I
SOURCE
= 200 µA
V
OL
, Output Low Voltage
2
0.4 V max DV
DD
= 5 V, I
SINK
= 1.6 mA
Floating State Leakage Current ±10 µA max
Floating State Output Capacitance ±10 pF typ
Data Output Coding Binary Unipolar Mode
Offset Binary Bipolar Mode
SYSTEM CALIBRATION
2
Full-Scale Calibration Limit 1.05 × FS V max
Zero-Scale Calibration Limit –1.05 × FS V min
Input Span 0.8 × FS V min
2.1 × FS V max
START-UP TIME
From Power-On 300 ms typ
From Power-Down Mode 1 ms typ
300 ms typ Oscillator Powered Down
POWER REQUIREMENTS
Power Supply Voltages AV
DD
and DV
DD
can be operated independently of each other.
AV
DD
–AGND 2.7/3.6 V min/max AV
DD
= 3 V nom
4.75/5.25 V min/max AV
DD
= 5 V nom
DV
DD
–DGND 2.7/3.6 V min/max DV
DD
= 3 V nom
4.75/5.25 V min DV
DD
= 5 V nom
DI
DD
(Normal Mode) 0.55 mA max DV
DD
= 3 V, 0.43 mA typ
0.65 mA DV
DD
= 5 V, 0.5 mA typ
AI
DD
(Normal Mode) 1.1 mA AV
DD
= 3 V or 5 V, 0.85 mA typ
DI
DD
(Power-Down Mode) 10 µA max DV
DD
= 3 V, 32.768 kHz Osc. Running
2 µA max DV
DD
= 3 V, Oscillator Powered Down
30 µA max DV
DD
= 5 V, 32.768 kHz Osc. Running
8 µA max DV
DD
= 5 V, Oscillator Powered Down
AI
DD
(Power-Down Mode) 1 µA max AV
DD
= 3 V or 5 V
Power Supply Rejection (PSR) Input Range = ±2.56 V, AIN = 1 V
Chop Disabled 70 dB min 95 dB typ
Chop Enabled 100 dB typ
NOTES
1
Temperature range is –40°C to +85°C.
2
Not production tested, guaranteed by design and/or characterization data at release.
3
Following a self-calibration this error will be in the order of the noise for the programmed gain and update selected. A system calibration will completely
remove this error.
4
Recalibration at any temperature will remove these errors.
5
I/O Port Logic Levels are with respect to AV
DD
and
AGND.
Specifications are subject to change without notice.
REV. 0
AD7708/AD7718
–9–
TIMING CHARACTERISTICS
1, 2
(AV
DD
= 2.7 V to 3.6 V or AV
DD
= 5 V ⴞ 5%; DV
DD
= 2.7 V to 3.6 V or DV
DD
= 5 V ⴞ 5%; AGND =
DGND = 0 V; XTAL = 32.768 kHz; Input Logic 0 = 0 V, Logic 1 = DV
DD
unless otherwise noted.
Limit at T
MIN
, T
MAX
Parameter (B Version) Unit Conditions/Comments
t
1
32.768 kHz typ Crystal Oscillator Frequency
t
2
50 ns min RESET Pulsewidth
Read Operation
t
3
0 ns min RDY to CS Setup Time
t
4
0 ns min CS Falling Edge to SCLK Active Edge Setup Time
3
t
5
4
0 ns min SCLK Active Edge to Data Valid Delay
3
60 ns max DV
DD
= 4.5 V to 5.5 V
80 ns max DV
DD
= 2.7 V to 3.6 V
t
5A
4, 5
0 ns min CS Falling Edge to Data Valid Delay
3
60 ns max DV
DD
= 4.5 V to 5.5 V
80 ns max DV
DD
= 2.7 V to 3.6 V
t
6
100 ns min SCLK High Pulsewidth
t
7
100 ns min SCLK Low Pulsewidth
t
8
0 ns min CS Rising Edge to SCLK Inactive Edge Hold Time
3
t
9
6
10 ns min Bus Relinquish Time after SCLK Inactive Edge
3
80 ns max
t
10
100 ns max SCLK Active Edge to RDY High
3, 7
Write Operation
t
11
0 ns min CS Falling Edge to SCLK Active Edge Setup Time
3
t
12
30 ns min Data Valid to SCLK Edge Setup Time
t
13
25 ns min Data Valid to SCLK Edge Hold Time
t
14
100 ns min SCLK High Pulsewidth
t
15
100 ns min SCLK Low Pulsewidth
t
16
0 ns min CS Rising Edge to SCLK Edge Hold Time
NOTES
1
Sample tested during initial release to ensure compliance. All input signals are specified with tr = tf = 5 ns (10% to 90% of DV
DD
) and timed from a voltage
level of 1.6 V.
2
See Figures 1 and 2.
3
SCLK active edge is falling edge of SCLK.
4
These numbers are measured with the load circuit of Figure 1 and defined as the time required for the output to cross the V
OL
or V
OH
limits.
5
This specification only comes into play if CS goes low while SCLK is low. It is required primarily for interfacing to DSP machines.
6
These numbers are derived from the measured time taken by the data output to change 0.5 V when loaded with the load circuit of Figure 1. The measured number is
then extrapolated back to remove effects of charging or discharging the 50 pF capacitor. This means that the times quoted in the timing characteristics are the true
bus relinquish times of the part and as such are independent of external bus loading capacitances.
7
RDY returns high after the first read from the device after an output update. The same data can be read again, if required, while RDY is high, although care should
be taken that subsequent reads do not occur close to the next output update.
Specifications subject to change without notice.
TO OUTPUT
PIN
50pF
I
SINK
I
SOURCE
1.6V
(1.6mA WITH DV
DD
= 5V
100␮A WITH DV
DD
= 3V)
(200␮A WITH DV
DD
= 5V
100␮A WITH DV
DD
= 3V)
Figure 1. Load Circuit for Timing Characterization
P1-P3P4-P6P7-P9P10-P12P13-P15P16-P18P19-P21P22-P24P25-P27P28-P30P31-P33P34-P36P37-P39P40-P42P43-P44

AD7708BRUZ-REEL

Mfr. #:
Buy AD7708BRUZ-REEL
Manufacturer:
Analog Devices Inc.
Description:
Analog to Digital Converters - ADC 16-Bit 8/10-Ch Low Vtg Low Pwr
Lifecycle:
New from this manufacturer.
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