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AD7708BRUZ-REEL

P1-P3P4-P6P7-P9P10-P12P13-P15P16-P18P19-P21P22-P24P25-P27P28-P30P31-P33P34-P36P37-P39P40-P42P43-P44
REV. 0
–28–
AD7708/AD7718
Operating Characteristics when Addressing the Mode and Control Registers
1. Any change to the MD bits will immediately reset the ADCs. A write to the MD2–MD0 bits with no change is also treated as a reset.
2. Once the MODE has been written with a calibration mode, the RDY bit (STATUS) is immediately reset and the calibration
commences. On completion the appropriate calibration registers are written, the bit in STATUS register is updated and the
MD2–MD0 bits are reset to 001 to indicate the ADC is back in idle mode.
3. Calibrations are performed with the maximum allowable SF value with chop enabled. SF register is reset to user configuration
after calibration with chop enabled. Calibrations are performed with the selected value of SF when chop is disabled.
ADC Control Register (ADCCON): (A3, A2, A1, A0 = 0, 0, 1, 0; Power-On-Reset = 07 Hex)
The ADC Control Register is an 8-bit register from which data can be read or to which data can be written. This register is used to
configure the ADC for range, channel selection, and unipolar or bipolar coding. Table XVI outlines the bit designations for the ADC
control register ADCCON7 through ADCCON0 indicate the bit location, ADCCON denoting the bits are in the ADC Control
Register. ADCCON7 denotes the first bit of the data stream. The number in brackets indicates the power-on/reset default status of
that bit.
Table XVI. ADC Control Register (ADCCON) Bit Designations
Bit Bit
Location Mnemonic Description
ADCCON7 CH3 ADC Channel Selection Bits. Written by the user to select either pseudo-differential or fully-
ADCCON6 CH2 differential input pairs used by the ADC as follows:
ADCCON5 CH1
ADCCON4 CH0
8-Channel Configuration 10-Channel Configuration
(CHCON = 0) (CHCON = 1)
Positive Negative Cal Register Positive Negative Cal Register
CH3 CH2 CH1 CH0 Input Input Pair Input Input Pair
0 0 0 0 AIN1 AINCOM 1 AIN1 AINCOM 1
0 0 0 1 AIN2 AINCOM 2 AIN2 AINCOM 2
0 0 1 0 AIN3 AINCOM 3 AIN3 AINCOM 3
0 0 1 1 AIN4 AINCOM 4 AIN4 AINCOM 4
0 1 0 0 AIN5 AINCOM 1 AIN5 AINCOM 5
0 1 0 1 AIN6 AINCOM 2 AIN6 AINCOM 1
0 1 1 0 AIN7 AINCOM 3 AIN7 AINCOM 2
0 1 1 1 AIN8 AINCOM 4 AIN8 AINCOM 3
1 0 0 0 AIN1 AIN2 1 AIN1 AIN2 1
1 0 0 1 AIN3 AIN4 2 AIN3 AIN4 2
1 0 1 0 AIN5 AIN6 3 AIN5 AIN6 3
1 0 1 1 AIN7 AIN8 4 AIN7 AIN8 4
1 1 0 0 AIN2 AIN2 1 AIN9 AIN10 5
1 1 0 1 AINCOM AINCOM 1 AINCOM AINCOM 1
1 1 1 0 REFIN(+) REFIN(–) 1 AIN9 AINCOM 4
1 1 1 1 OPEN OPEN 1 AIN10 AINCOM 5
ADCCON3 U/B Unipolar/Bipolar Bit.
Set by user to enable unipolar coding i.e., zero differential input will result in 000000hex
output and a full-scale differential input will result in FFFFFF Hex output when operated in
24-bit mode.
Cleared by user to enable bipolar coding, Negative full-scale differential input will result in an
output code of 000000 Hex, zero differential input will result in an output code of 800000 Hex
and a positive full-scale differential input will result in an output code of FFFFFF Hex.
ADCCON7 ADCCON6 ADCCON5 ADCCON4 ADCCON3 ADCCON2 ADCCON1 ADCCON0
CH3 (0) CH2 (0) CH1 (0) CH0 (0) U/B (0) RN2 (1) RN1 (1) RN0 (1)
REV. 0
AD7708/AD7718
–29–
AD0C2 RN2 ADC Range Bits
AD0C1 RN1 Written by the user to select the ADC input range as follows
AD0C0 RN0 RN2 RN1 RN0 Selected ADC Input Range (VREF = 2.5 V)
000±20 mV
001±40 mV
010±80 mV
011±160 mV
100±320 mV
101±640 mV
110±1.28 V
111±2.56 V
Filter Register (A3, A2, A1, A0 = 0, 0, 1, 1; Power-On Reset = 45Hex)
The Filter Register is an 8-bit register from which data can be read or to which data can be written. This register determines the
amount of averaging performed by the sinc filter. Table XVII outlines the bit designations for the Filter Register. FR7 through FR0
indicate the bit location, FR denoting the bits are in the Filter Register. FR7 denotes the first bit of the data stream. The number in
brackets indicates the power-on/reset default status of that bit. The number in this register is used to set the decimation factor and
thus the output update rate for the ADCs. The filter register cannot be written to by the user the ADC is active. The update rate is
used for the ADCs is calculated as follows:
f f CHOP Enabled CHOP
f
SF
f CHOP Disabled CHOP
ADC MOD
ADC MOD
=× =
=
×
×=
()
()
1
3
0
1
8
1
where
f
ADC
= ADC Output Update Rate,
f
MOD
= Modulator Clock Frequency = 32.768 kHz,
SF = Decimal Value Written to SF Register.
Table XVII. Filter Register Bit Designations
7RF6RF5RF4RF3RF2RF1RF0RF
)0(7FS6FS)1(5FS)0(4FS)0(3FS)0()1(2FS)0(1FS)1(0FS
The allowable range for SF is 13 decimal to 255 decimal with chop enabled, and the allowable SF range when chop is disabled is 03
decimal to 255 decimal. Examples of SF values and corresponding conversion rate (f
ADC
) and time (t
ADC
) are shown in Table XVIII.
It should be noted that optimum performance is obtained when operating with chop enabled. When chopping is enabled (CHOP = 0),
the filter register is loaded with FF HEX during a calibration cycle. With chop disabled (CHOP =1), the value in the filter register is
used during calibration.
Table XVIII. Update Rate vs. SF Word
CHOP Enabled CHOP Disabled
SF (Dec) SF (Hex) f
ADC
(Hz) t
ADC
(ms) f
ADC
(Hz) t
ADC
(ms)
03 03 N/A N/A 1365.33 0.732
13 0D 105.3 9.52 315 3.17
69 45 19.79 50.34 59.36 16.85
255 FF 5.35 186.77 16.06 62.26
Table XVI. ADC Control Register (ADCCON) Bit Designations (continued)
REV. 0
–30–
AD7708/AD7718
I/O Control Register (IOCON): (A3, A2, A1, A0 = 0, 1, 1, 1; Power-On-Reset = 00Hex)
The IOCON Register is an 8-bit register from which data can be read or to which data can be written. This register is used to con-
trol and configure the I/O port. Table XIX outlines the bit designations for this register. IOCON7 through IOCON0 indicate the
bit location, IOCON denoting the bits are in the I/O Control Register. IOCON7 denotes the first bit of the data stream. The num-
ber in brackets indicates the power-on/reset default status of that bit. A write to the IOCON register has immediate effect and does
not reset the ADCs.
7NOCOI6NOCOI5NOCOI4NOCOI3NOCOI2NOCOI1NOCOI0NOCOI
)0(0)0()0(RID2PRID1P)0(0)0()0(0)0(TAD2P)0(TAD1P
Table XIX. IOCON (I/O Control Register) Bit Designations
Bit Bit
Location Mnemonic Description
IOCON7 0 This bit should always be cleared. Reserved for future use.
IOCON6 0 This bit should always be cleared. Reserved for future use.
IOCON5 P2DIR P2, I/O Direction Control Bit.
Set by user to enable P2 as an output.
Cleared by user to enable P2 as an input. There are weak pull-ups internally when enabled
as an input.
IOCON4 P1DIR P1, I/O Direction Control Bit.
Set by user to enable P1 as an output.
Cleared by user to enable P1 as an input. There are weak pull-ups internally when enabled
as an input.
IOCON3 0 This bit should always be cleared. Reserved for future use.
IOCON2 0 This bit should always be cleared. Reserved for future use.
IOCON1 P2DAT Digital I/O Port (P1) Data Bit.
The readback value of this bit indicates the status of the pin regardless of whether this pin is
configured as an input or an output. The value written to this data bit will appear at the
output port when the I/O pin is enabled as an output.
IOCON0 P1DAT Digital I/O port (P1) Data Bit.
The readback value of this bit indicates the status of the pin, regardless of whether this pin is
configured as an input or an output. The value written to this data bit will appear at the
output port when the I/O pin is enabled as an output.
ADC Data Result Register (DATA): (A3, A2, A1, A0 = 0, 1, 0, 0; Power-On-Reset = 000000Hex)
The conversion result for the selected ADC channel is stored in the ADC data register (DATA). This register is 16 bits wide on the
AD7708 and 24 bits wide on the AD7718. This is a read only register. On completion of a read from this register the RDY bit in
the status register is cleared. These ADCs can be operated in either unipolar or bipolar mode of operation.
Unipolar Mode
In unipolar mode of operation the output coding is straight binary. With an analog input voltage of 0 V the output code is 0000Hex
for the AD7708 and 000000Hex for the AD7718. With an analog input voltage of 1.024 V
REF
/Gain the output code is FFFFHex
for the AD7708 and FFFFFF Hex for the AD7718. The output code for any analog input voltage can be represented as follows:
Code = (AIN × GAIN × 2
N
)/(1.024 × V
REF
)
where
AIN is the analog input voltage and
N = 16 for the AD7708 and N = 24 for the AD7718.
P1-P3P4-P6P7-P9P10-P12P13-P15P16-P18P19-P21P22-P24P25-P27P28-P30P31-P33P34-P36P37-P39P40-P42P43-P44

AD7708BRUZ-REEL

Mfr. #:
Buy AD7708BRUZ-REEL
Manufacturer:
Analog Devices Inc.
Description:
Analog to Digital Converters - ADC 16-Bit 8/10-Ch Low Vtg Low Pwr
Lifecycle:
New from this manufacturer.
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